T7570-ML2-TR データシートの表示（PDF） - Agere -> LSI Corporation

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T7570-ML2-TR

Programmable PCM codec with hybrid-balance filter.

Agere -> LSI Corporation 

Data Sheet

October 1996

T7570 Programmable PCM Codec

with Hybrid-Balance Filter

Pin Information (continued)

Table 1. Pin Description (continued)

Pin

Symbol

Type

22

FSX

I

23

IL5

I/O

24

IL4

I/O

25

IL1

I/O

26

IL0

I/O

27

VDD

—

28

VFXI

I

Name/Description

Transmit Frame-Sync Input. A pulse or square-wave waveform

with an 8 kHz repetition rate is applied to this input to define the start

of the transmit time slot assigned to this device (nondelayed frame

mode) or the start of the transmit frame (delayed frame mode using

the internal time-slot assignment counter). If only the receive chan-

nel is being used, it is still necessary to apply the transmit frame-

sync every frame.

Interface Latch. See pin 6.

5 V ± 5% Power Supply.

Transmit Analog High-Impedance Input. Voice-frequency signals

present on this input are encoded as an A-law or µ-law PCM bit

stream and are shifted out on the selected DX pin.

Functional Description

Powerup Initialization

When power is first applied, powerup reset circuitry ini-

tializes the T7570 and puts it into the powerdown state.

The gain control registers for the transmit and receive

gain sections are programmed to off, the hybrid-

balance circuit is turned off, the power amp is disabled,

and the device is in the nondelayed timing mode. The

latch direction register (LDR) is preset with all IL pins

programmed as inputs, placing the interface pins in a

high-impedance state. The CI is ready for the first con-

trol byte of the initialization sequence. Other initial

states in the control register are indicated in the Control

Register Instruction section under Programmable

Functions.

A reset to these same initial conditions can also be

forced by driving the MR pin momentarily high for at

least 1 µs. This can be done either on powerup or pow-

erdown. For normal operation, this pin must be pulled

low.

The desired modes for all programmable functions can

be initialized via the serial control port prior to a pow-

erup command.

Powerdown State

Following a period of activity in the powerup state, the

powerdown state can be entered by writing any of the

control instructions into the serial control port with the

P bit set to 1, as indicated in Table 2.

The powerdown instruction can be included within any

other instruction code. It is recommended that the chip

be powered down before executing any instructions. In

the powerdown state, all nonessential circuitry is de-

activated and the DX0 and DX1 outputs are in the high-

impedance condition.

The coefficients stored in the hybrid-balance circuit and

the gain control registers, the data in the LDR and ILR,

and all control bits remain unchanged in the power-

down state unless changed by writing new data via the

serial control port, which remains active. The outputs of

the interface latches also remain active, maintaining

the ability to monitor and control interface circuits like a

SLIC.

Transmit Filter and Encoder

The transmit section input, VFXI, provides a high-

impedance load to the line-interface circuit. The input

signal is summed with the internal hybrid cancellation

signal. The resulting signal is the input to a programma-

ble gain or attenuation amplifier that is controlled by the

contents of the transmit gain register (see Programma-

ble Functions section). The signal is then passed

through an antialiasing filter followed by a fifth-order,

low-pass and third-order, high-pass, switched-capacitor

filter. After the filter, the A/D converter translates

the signal into PCM data for transmission. The A/D

Lucent Technologies Inc.

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