RC5054 データシートの表示（PDF） - Fairchild Semiconductor

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RC5054

Programmable Synchronous DC-DC Converter Controller for Low Voltage Microprocessors

Fairchild Semiconductor 

RC5054A

OSC

PWM

COMPARATOR

-

DVOSC

+

VIN

DRIVER

DRIVER

LO

VOUT

PHASE

CO

ZFB

VE/A

-

+

ZIN

ERROR REFERENCE

AMP

ESR

(PARASITIC)

DETAILED COMPENSATION COMPONENTS

C2

C1 R2

ZFB

VOUT

ZIN

C3 R3

R1

COMP

FB

-

+

RC5054

DACOUT

Figure 5. Voltage-Mode Buck

Converter Compensation Design

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output filter (LO and CO), with a double pole

break freaquency at FLC and a zero at FESR. The DC Gain of

the modulator is simply the input voltage (VIN) divided by

the peak-to-peak oscillator voltage ∆VOSC.

Modulator Break Frequency Equations

FLC

=

------------------1------------------

2π • LO • CO

FESR = 2----π-----•----E----S-1---R-----•----C----O--

The compensation network consists of the error amplifier

(internal to the RC5054A) and the impedance networks ZIN

and ZFB. The goal of the compensation network is to provide

a closed loop transfer function with the highest 0dB crossing

frequency (f0dB) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f0dB and

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 5. Use these guidelines for

locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)

PRODUCT SPECIFICATION

3. Place 2ND Zero at Filter’s Double Pole

4. Place 1ST Pole at the ESR Zero

5. Place 2ND Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Compensation Break Frequency Equations

FZ1 = 2----π-----•----R--1--2-----•----C----1--

FP1

=

-------------------------1--------------------------

2π • R2 • -CC----11----+-•----CC----2-2-

FZ2 = 2----π-----•----(--R-----1----+-1----R----3----)---•----C-----3-

FP2 = 2----π-----•----R--1--3-----•----C----3--

Figure 6 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual Modulator Gain has a high

gain peak due to the high Q factor of the output filter and is

not shown in Figure 6. Using the above guidelines should

give a Compensation Gain similar to the curve plotted.

The open loop error amplifier gain bounds the compensation

gain. Check the compensation gain at FP2 with the capabili-

ties of the error amplifier. The Closed Loop Gain is con-

structed on the log-log graph of Figure 6 by adding the

Modulator Gain (in dB) to the Compensation Gain (in dB).

This is equivalent to multiplying the modulator transfer func-

tion to the compensation transfer function and plotting the

gain.

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) over-

all loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

100

FZ1 FZ2 FP1 FP2

80

60

OPEN LOOP

ERROR AMP GAIN

40

20LOG

20 (R2/R1)

0

20LOG

(VIN / ∆VOSC)

-20

MODULATOR

GAIN

-40

-60

FLC

FESR

10 100 1K 10K 100K

COMPENSATION

GAIN

CLOSED LOOP

GAIN

1M 10M

FREQUENCY (Hz)

Figure 6. Asymptotic Bode Plot of Converter Gain

8

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