LU3X34FTR-HS128-DB データシートの表示（PDF） - Agere -> LSI Corporation

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LU3X34FTR-HS128-DB

Quad 3 V 10/100 Ethernet Transceiver TX/FX

Agere -> LSI Corporation 

Preliminary Data Sheet

July 2000

LU3X34FTR

Quad 3 V 10/100 Ethernet Transceiver TX/FX

Pin Descriptions (continued)

Table 4. MII Interface (RMII Mode) (continued)

Pin No.

90

78

Pin Name*

RMII_RXER_1

CRS_DV_2/PHYAD[3]

I/O

O

I/O↓

74, 75

76, 77

86

67

RMII_TXD_2[0:1]

RMII_RXD_2[0:1]

RMII_RXER_2

CRS_DV_3/PHYAD[4]

I/O

O

O

I/O↓

54, 55

RMII_TXD_3[0:1]

I

56, 57

RMII_RXD_3[0:1]

I/O

69

RMII_RXER_3

O

59

MDIO

I/O

58

MDC

I

65, 87, 70

RESERVED

O

* Smaller font indicates that the pin has multiple functions.

Pin Description

Receiver Error Output for Port 1.

CRS_DV Output for Port 2. During reset, this is an

input pin for PHY_address[3] configuration. This pin

has an internal 40 kΩ pull-down resistor that sets the

PHY_AD[3] to a 0 without an external component.

After reset, CRS_DV output for port 2 and is

asserted only during receive activity.

Transmit Data for Port 2.

Receive Data for Port 2.

Receiver Error for Port 2.

CRS_DV Output for Port 3. During reset, this is an

input pin for PHY_address[4] configuration. This pin

has an internal 40 kΩ pull-down resistor that sets the

PHY_AD[4] to a 0 without an external component.

After reset, CRS_DV output for port 3 and is

asserted only during receive activity.

Transmit Data for Port 3.

Receive Data for Port 3.

Receive Error Output for Port 3.

Management Data for Serial Register Access.

Management Clock. Max clock rate = 2.5 MHz.

Reserved. Leave this pin float.

Table 5. MII Interface (SMII Mode)

Pin No.

113

112

110

101

Pin Name*

SMII_SYNC

SMII_TXD_0

SMII_RXD_0

SMII_EN

98

96

67, 78, 94

SMII_TXD_1

SMII_RXD_1

PHYAD[4:2]

54

SMII_TXD_3

56

SMII_RXD_3

74

SMII_TXD_2

76

SMII_RXD_2

59

MDIO

I/O

Pin Description

I

SMII Sync Input.

I

Transmit Data for Port 0.

I/O

Receive Data for Port 0.

I/O↓ SMII_EN. This pin must be pulled high at powerup or

reset to enable SMII mode. This input has an inter-

nal 40 kΩ pull-down resistor.

I/O

Transmit Data for Port 1.

O

Receive Data for Port 1.

I/O

Configure PHY Address. These pins configure

PHY_address 4 through 2 at powerup or reset. Each

of these pins has an internal 40 kΩ pull-down resis-

tor that sets the corresponding PHY_AD to 0, with-

out an external component.

I

Transmit Data for Port 3.

I/O

Receive Data for Port 3.

I/O

Transmit Data for Port 2.

O

Receive Data for Port 2.

I/O

Management Data for Serial Register Access. An

external resistive pull-up is needed on this pin.

Lucent Technologies Inc.

9

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