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MC14C89AB データシートの表示(PDF) - Motorola => Freescale

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MC14C89AB
Motorola
Motorola => Freescale Motorola
MC14C89AB Datasheet PDF : 6 Pages
1 2 3 4 5 6
Order this document by MC14C89B/D
MC14C89B, AB
Quad Low Power
Line Receivers
The MC14C89B and MC14C89AB are low monolithic quad line receivers
using bipolar technology, which conform to the EIA–232–E, EIA–562 and
CCITT V.28 Recommendations. The outputs feature LSTTL and CMOS
compatibility for easy interface to +5.0 V digital systems. Internal
time–domain filtering eliminates the need for external filter capacitors in most
cases.
The MC14C89B has an input hysteresis of 0.35 V, while the MC14C89AB
hysteresis is 0.95 V. The response control pins allow adjustment of the
threshold level if desired. Additionally, an external capacitor may be added
for additional noise filtering.
The MC14C89B and MC14C89AB are available in both a 14 pin
dual–in–line plastic DIP and SOIC package.
Features:
Low Power Consumption
Meets EIA–232–E, EIA–562, and CCITT V.28 Recommendations
TTL/CMOS Compatible Outputs
Standard Power Supply: + 5.0 V ±10%
Pin Equivalent to MC1489, MC1489A, TI’s SN75C189/A, SN75189/A
and National Semiconductor’s DS14C89/A
External Filtering Not Required in Most Cases
Threshold Level Externally Adjustable
Hysteresis: 0.35 V for MC14C89B, 0.95 V for MC14C89AB
Available in Plastic DIP, and Surface Mount Packaging
Operating Ambient Temperature: –40° to +85°C
Representative Block Diagram
(Each Receiver)
VCC
Input
QUAD LOW POWER
LINE RECEIVERS
SEMICONDUCTOR
TECHNICAL DATA
P SUFFIX
PLASTIC PACKAGE
CASE 646
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
PIN CONNECTIONS
Input A 1
Response
Control A
2
Output A 3
Input B 4
Response
Control B
5
Output B 6
Ground 7
14 VCC
13 Input D
12
Response
Control D
11 Output D
10 Input C
9
Response
Control C
8 Output C
(Top View)
Response
Control
MOTOROLA ANALOG IC DEVICE DATA
Output
ORDERING INFORMATION
Device
Operating
Temperature Range Package
MC14C89BP
Plastic DIP
MC14C89ABP TA = – 40° to +85°C Plastic DIP
MC14C89ABD
SO–14
© Motorola, Inc. 1996
Rev 0
1

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