T7504-ML データシートの表示（PDF） - Agere -> LSI Corporation
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T7504-ML Datasheet PDF : 18 Pages
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Data Sheet
March 1999
T7504 and T5504 Quad PCM Codecs with Filters
Features
s 5 V only
s Low-power, latch-up-free CMOS technology
— 37 mW/channel typical operating power
dissipation
— 1 mW/channel typical powerdown dissipation
s Automatic master clock frequency selection
— 2.048 MHz or 4.096 MHz
s On-chip sample and hold, autozero, and precision
voltage reference
s Differential architecture for high noise immunity
and power supply rejection
s Flexible time-slotted PCM interface
— 2.048 MHz or 4.096 MHz data rate
s Meets or exceeds ITU-T G.711—G.714 require-
ments and VF characteristics of D3/D4 (as per
Lucent Technologies PUB43801)
s Operating temperature range: –40 °C to +85 °C
s µ-law/A-law companding selectable
Description
The T7504 and T5504 devices are single-chip, four-
channel µ-law/A-law PCM codecs with filters. These
integrated circuits provide analog-to-digital and
digital-to-analog conversion. They provide the
transmit and receive filtering necessary to interface a
voice telephone circuit to a time-division multiplexed
system. These devices are available in 28-pin
PLCCs. The T7504 is also available in a 44-pin
MQFP.
The T5504 differs from the T7504 in its timing mode.
The T5504 operates in the nondelay timing mode
(digital data valid when frame sync goes high), and
the T7504 operates in the delayed timing mode
(digital data is valid one clock cycle after frame sync
goes high) (see Figures 6—9).
GSX0
VFXIN0
VFRO0
GSX1
VFXINF1
VFRO1
GSX2
VFXIN2
VFRO2
GSX3
VFXIN3
VFRO3
–
+
+2.4 V
FILTER
NETWORK
CHANNEL 0
ENCODER
PCM
INTERFACE
DX
DR
FSX0
FSX1
FSX2
FSX3
FSEP
GNDD
FILTER
NETWORK
DECODER
CHANNEL 1
CHANNEL 2
CHANNEL 3
POWERDOWN
CONTROL
INTERNAL TIMING
& CONTROL
BIAS
CIRCUITRY
&
REFERENCE
MCLK
ASEL
VDD (2)
VDD (2) (MQFP ONLY)
GNDA (4) (PLCC ONLY)
GNDA (5) (MQFP ONLY)
Figure 1. Block Diagram For 28-Pin DIP and 28-Pin PLCC
5-3579.d(C)
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