TLIU04C1 データシートの表示（PDF） - Agere -> LSI Corporation

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TLIU04C1

Quad T1/E1 Line Interface

Agere -> LSI Corporation 

TLIU04C1 Quad T1/E1 Line Interface

Advance Data Sheet, Rev. 2

April 1999

Description

Microprocessor Mode

The TLIU04C1 is a quad line interface containing four

line transmit and receive channels for use in both North

American (T1/DS1) and European (E1/CEPT) applica-

tions. The line interface unit has the same functions as

the Lucent T7698.

The device can operate in either of two modes, chosen

by the logic state of a control pin. A direct logic control

mode provides the ability to define the architecture, ini-

tiate loopbacks, and monitor alarms without connecting

to a microprocessor by setting the logic levels on con-

trol pins. The microprocessor mode uses a parallel

microprocessor interface to allow the user to configure

the device. The interface is compatible with many com-

mercially available microprocessors. The block dia-

grams of the microprocessor and direct logic modes

are shown in Figure 2 and Figure 25, respectively.

The block diagram of the line interface unit is shown in

Figure 3 on page 19 (it is repeated as Figure 26). The

line receiver performs clock and data recovery using a

fully integrated digital phase-locked loop. This digital

implementation prevents false lock conditions that are

common when recovering sparse data patterns with

analog phase-locked loops.

Equalization circuitry in the receiver provides a high

level of interference immunity. As an option, the raw

sliced data (no retiming) can be output on the receive

data pins. Transmit equalization is implemented with

low-impedance output drivers that provide shaped

waveforms to the transformer, guaranteeing template

conformance. The quad device will interface to the digi-

tal cross connect (DSX) at lengths of up to 655 ft. for

DS1 operation or to line impedances of 75 Ω or 120 Ω

for CEPT operation.

A selectable jitter attenuator may be placed in the

receive signal path for low-bandwidth line-synchronous

applications, or it may be placed in the transmit path for

multiplexer applications where DS1/CEPT signals are

demultiplexed from higher rate signals. The jitter atten-

uator will perform the clock smoothing required on the

resulting demultiplexed gapped clock.

Overview

The TLIU04C1 device has the ability to operate in

either a microprocessor mode or a direct logic control

mode. The CMODE pin is used to determine the oper-

ating mode. To configure the device for microprocessor

mode, the CMODE pin is pulled high.

The device is equipped with a microprocessor interface

that can operate with most commercially available

microprocessors. Inputs MPMUX and MPMODE

(pins 108 and 110) are used to configure this interface

into one of four possible modes, as shown in Table 3.

The MPMUX setting selects either a multiplexed 8-bit

address/data bus (AD[7:0]) or a demultiplexed 4-bit

address bus (A[3:0]) and an 8-bit data bus (AD[7:0]).

The MPMODE setting selects the associated set of

control signals required to access a set of registers

within the device.

When the microprocessor interface is configured to

operate in the multiplexed address/data bus modes

(MPMUX = 1), the user has access to an internal chip

select function that allows the microprocessor to selec-

tively read/write a specific TLIU04C1 in a multiple

TLIU04C1 environment (see the Internal Chip Select

Function section, page 16).

The microprocessor interface can operate at speeds up

to 16.384 MHz in interrupt-driven or polled mode with-

out requiring any wait-states. For microprocessors

operating at greater than 16.384 MHz, the

RDY_DTACK output is used to introduce wait-states in

the read/write cycles.

In the interrupt-driven mode, one or more device

alarms will assert the active-high INT output (pin 114)

once per alarm activation. After the microprocessor

reads the alarm status registers, the INT output will

deassert. In the polled mode, however, the micropro-

cessor monitors the various device alarm status by

periodically reading the alarm status registers without

the use of INT. A variety of LIU mask controls are avail-

able for control of the INT pin.

8

Lucent Technologies Inc.

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