MAX4523CSE(2001) データシートの表示（PDF） - Maxim Integrated
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MAX4523CSE Datasheet PDF : 14 Pages
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Quad, Low-Voltage, SPST Analog Switches
Test Circuits/Timing Diagrams
MAX4521
MAX4522
MAX4523
SWITCH
INPUT
VCOM
COM
LOGIC
INPUT
IN, EN
GND
0
V+
V+
NO
or NC
V-
V-
SWITCH
OUTPUT
VOUT
RL
CL
300Ω
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VCOM
RL
RL + RON
Figure 1. Switching Time
+3V
LOGIC
INPUT 0
50%
tr < 20ns
tf < 20ns
SWITCH 0
OUTPUT
tOFF
VOUT 0.9 x V0UT
tON
0.9 x VOUT
LOGIC INPUT WAVEFORMS INVERTED FOR EN AND SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
MAX4523
V+
VCOM1
VCOM2
COM1
COM2
IN1, 2
V+
NO
NC
VOUT2 RL1
RL2
CL2
LOGIC
INPUT
GND
V-
V-
RL = 300Ω
CL INCLUDES FIXTURE AND STRAY CAPACITANCE. CL = 35pF
Figure 2. Break-Before-Make Interval (MAX4523 only)
VOUT1
CL1
LOGIC +3V
INPUT
0
SWITCH
OUTPUT 1
(VOUT1)
0
SWITCH
OUTPUT 2
(VOUT2)
0
50%
0.9 x V0UT1
0.9 x VOUT2
tD
tD
MAX4521
MAX4522
MAX4523
RGEN
COM
VGEN
GND
V+
V+
NC or
NO
IN V-
VOUT
CL
VOUT
IN
OFF
∆VOUT
OFF
ON
V-
VIN = +3V
ON
OFF
OFF
IN
Q = (∆VOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 3. Charge Injection
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