QL901M-6PS680I データシートの表示（PDF） - QuickLogic Corporation

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QL901M-6PS680I

QuickMIPS ESP Family

QuickLogic Corporation 

The ECU block can be configured for eight arithmetic functions via an instruction as shown in Table 4.

The modes for the ECU block are dynamically reprogrammable through the Instruction Set Sequencer.

Table 4: ECU Mode Select Criteria

Instruction Set

Operation

0

0

0

Multiply

0

0

1

Multiply - Add

0

1

0

Accumulate

0

1

1

Add

1

0

0

Multiply (registered)

1

0

1

Multiply - Add (registered)

1

1

0

Multiple - Accumulate

1

1

1

Add (registered)

The Sequencer can be a variety of logic operators, such as a FIFO loaded with various algorithms, an

external software driven algorithm, or an internal state machine. This flexibility allows the designer to

reconfigure the ECU for algorithmic intensive applications in which functions change on the next clock

cycle, such as adaptive filtering.

3.0 Design Flow

The QuickMIPS design flow, similar to ASIC design flow, is shown in Figure 3.

MIPS Programming System Configuration Customer IP Design in FPGA

Compiler,

Assembler, Linker

Global Register

Configuration

RTL

QuickIP Models

Debugger

Synthesis

Synthesis Lib

EJTAG

Board-level

Support Package

QuickMIPS

System

Model

Place & Route

Timing Analysis

Timing Lib

Final Netlist

& Timing

QuickIP Netlist

Full-System

Functional Co-simulation

with Timing

Chip Programming

Figure 3: QuickMIPS Hardware/Software Co-Development Flow

QL901M QuickMIPS™ Data Sheet Rev B

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