QL901M-6PS680I データシートの表示（PDF） - QuickLogic Corporation

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QL901M-6PS680I

QuickMIPS ESP Family

QuickLogic Corporation 

A typical design process goes through the flow shown above. After passing postlayout simulation,

QuickMIPS devices can be programmed for testing on the hardware testbench. Because QuickLogic

devices are One-Time-Programmable (OTP), it is recommended that these devices are programmed only

after they pass postlayout simulation to minimize development cost and reduce bench debugging time.

The QuickMIPS design flow is supported by QuickLogic's QuickWorks™ (for Microsoft Windows) and

QuickTool™ (for UNIX) design software suites version 9.2 and up. Many third-party synthesis and

simulation tools are also supported. The QuickWorks software suite can be downloaded from

QuickLogic's Web site (www.quicklogic.com). Please contact a QuickLogic sales representative to

obtain a license or get QuickTool software.

Both Verilog and VHDL design methodologies are fully supported. The flow described below assumes

that the QuickWorks or QuickTool 9.2 software has been installed.

3.1 Simulation

QuickLogic provides the system simulation environment. This environment includes the QuickMIPS

VMC model, ROM and RAM models, reset and clock generation, boot code, and sample programs (read

and write to memory). This environment allows customers to focus on their RTL code and not have to

worry about bringing up the system simulation environment.

The simulation behavior of the QuickMIPS ESP core is provided by the VMC model. VMC (Verilog

Model Compiler) is a tool from Synopsys that compiles Verilog RTL (Register-Transfer-Level) code into

binary code. A VMC model (the binary code) implements the same logic functions as the RTL code while

providing IP protection. In simulation, it communicates to the simulator via PLI (Programmable

Language Interface) for Verilog or FLI (Foreign Language Interface) for VHDL.

Because of the VMC model, the Silos III Verilog simulator and Active-HDL VHDL simulator bundled in

QuickWorks are not supported in QuickMIPS simulation flow. A third-party simulator must be used. The

currently supported simulators include:

• Verilog simulators: Verilog-XL, NC Verilog, VCS, ModelSim

• VHDL simulators: VSS, ModelSim

3.2 Synthesis

Synthesis is the process of turning the HDL code describing the fabric behavior into gates. Three third-

party synthesis tools are supported:

• Synplify-Lite from Synplicity (bundled in QuickWorks)

• Exemplar Leonardo Spectrum

• Synopsys Design Compiler

Refer to the corresponding QuickNotes on the QuickLogic support Web site for further information.

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