CD4073BMS データシートの表示（PDF） - Intersil
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CD4073BMS Datasheet PDF : 10 Pages
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CD4073BMS, CD4081BMS
CD4082BMS
January 1993
CMOS AND Gate
Features
Pinout
• High-Voltage Types (20V Rating)
• CD4073BMS Triple 3-Input AND Gate
CD4073BMS
TOP VIEW
• CD4081BMS Quad 2-Input AND Gate
• CD4082BMS Dual 4-Input AND Gate
• Medium Speed Operation:
- tPLH, tPHL = 60ns (typ) at VDD = 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
A1
B2
D3
E4
F5
K=D•E•F 6
VSS 7
14 VDD
13 G
12 H
11 I
10 L = G • H • I
9 J=A•B•C
8C
CD4081BMS
TOP VIEW
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4073BMS, CD4081BMS and CD4082BMS AND gates
provide the system designer with direct implementation of
the AND function and supplement the existing family of
CMOS gates.
A1
B2
J=A•B 3
K=C•D 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G • H
10 L = E • F
9F
8E
The CD4073BMS, CD4081BMS and CD4082BMS are supplied
in these 14 lead outline packages:
Braze Seal DIP
*H4Q †H4H
Frit Seal DIP
*H1B
Ceramic Flatpack
*H3W
*CD4073B, CD4081B †CD4082B
CD4082BMS
TOP VIEW
J=A•B•C•D 1
D2
C3
B4
A5
NC 6
VSS 7
14 VDD
13 K = E • F • G • H
12 H
11 G
10 F
9E
8 NC
NC = NO CONNECTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-433
File Number 3324
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