HS-1135RH(1999) データシートの表示（PDF） - Intersil

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HS-1135RH
(Rev.:1999)

Radiation Hardened, High Speed, Low Power Current Feedback Amplifier with Programmable Output Limiting

Intersil 

HS-1135RH

Clamp Operation

General

The HS-1135RH features user programmable output clamps

to limit output voltage excursions. Clamping action is obtained

by applying voltages to the VH and VL terminals (pins 8 and 5)

of the amplifier. VH sets the upper output limit, while VL sets

the lower clamp level. If the amplifier tries to drive the output

above VH, or below VL, the clamp circuitry limits the output

voltage at VH or VL ( the clamp accuracy), respectively. The

low input bias currents of the clamp pins allow them to be

driven by simple resistive divider circuits, or active elements

such as amplifiers or DACs.

Clamp Circuitry

Figure 1 shows a simplified schematic of the HS-1135RH

input stage, and the high clamp (VH) circuitry. As with all

current feedback amplifiers, there is a unity gain buffer (QX1

- QX2) between the positive and negative inputs. This buffer

forces -IN to track +IN, and sets up a slewing current of (V-

IN - VOUT)/RF. This current is mirrored onto the high

impedance node (Z) by QX3-QX4, where it is converted to a

voltage and fed to the output via another unity gain buffer. If

no clamping is utilized, the high impedance node may swing

within the limits defined by QP4 and QN4. Note that when the

output reaches it’s quiescent value, the current flowing

through -IN is reduced to only that small current (-IBIAS)

required to keep the output at the final voltage.

V+

QP3

QP4

50K

QN2

(30K R1

+IN

QP1

ICLAMP

Z

V-

FOR VL)

+1

V+

QN1

QP2

QN5

QN6

QP6

VH

200Ω

QN3

QN4 QP5

V-

-IN

RF

(EXTERNAL)

VOUT

FIGURE 1. HS-1135RH SIMPLIFIED VH CLAMP CIRCUITRY

Tracing the path from VH to Z illustrates the effect of the

clamp voltage on the high impedance node. VH decreases

by 2VBE (QN6 and QP6) to set up the base voltage on QP5.

QP5 begins to conduct whenever the high impedance node

reaches a voltage equal to QP5’s base + 2VBE (QP5 and

QN5). Thus, QP5 clamps node Z whenever Z reaches VH.

R1 provides a pull-up network to ensure functionality with

the clamp inputs floating. A similar description applies to the

symmetrical low clamp circuitry controlled by VL.

When the output is clamped, the negative input continues to

source a slewing current (ICLAMP) in an attempt to force the

output to the quiescent voltage defined by the input. QP5 must

sink this current while clamping, because the -IN current is

always mirrored onto the high impedance node. The clamping

current is calculated as (V-IN - VOUT)/RF. As an example, a

unity gain circuit with VIN = 2V, VH = 1V, and RF = 510Ω would

have ICLAMP = (2-1)/510Ω = 1.96mA. Note that ICC will

increase by ICLAMP when the output is clamp limited.

Clamp Accuracy

The clamped output voltage will not be exactly equal to the

voltage applied to VH or VL. Offset errors, mostly due to VBE

mismatches, necessitate a clamp accuracy parameter which is

found in the device specifications. Clamp accuracy is a function

of the clamping conditions. Referring again to Figure 1, it can

be seen that one component of clamp accuracy is the VBE

mismatch between the QX6 transistors, and the QX5 transistors.

If the transistors always ran at the same current level there

would be no VBE mismatch, and no contribution to the

inaccuracy. The QX6 transistors are biased at a constant

current, but as described earlier, the current through QX5 is

equivalent to ICLAMP. VBE increases as ICLAMP increases,

causing the clamped output voltage to increase as well. ICLAMP

is a function of the overdrive level (V-IN -VOUTCLAMPED) and

RF, so clamp accuracy degrades as the overdrive increases, or

as RF decreases. As an example, the specified accuracy of

±60mV for a 2X overdrive with RF = 510Ω degrades to ±220mV

for RF = 240Ω at the same overdrive, or to ±250mV for a 3X

overdrive with RF = 510Ω.

Consideration must also be given to the fact that the clamp

voltages have an effect on amplifier linearity. The

“Nonlinearity Near Clamp Voltage” curve in the data sheet

illustrates the impact of several clamp levels on linearity.

Clamp Range

Unlike some competitor devices, both VH and VL have usable

ranges that cross 0V. While VH must be more positive than VL,

both may be positive or negative, within the range restrictions

indicated in the specifications. For example, the HS-1135RH

could be limited to ECL output levels by setting VH = -0.8V and

VL = -1.8V. VH and VL may be connected to the same voltage

(GND for instance) but the result won’t be in a DC output

voltage from an AC input signal. A 150 - 200mV AC signal will

still be present at the output.

Recovery from Overdrive

The output voltage remains at the clamp level as long as the

overdrive condition remains. When the input voltage drops

below the overdrive level (VCLAMP/AVCL) the amplifier will

return to linear operation. A time delay, known as the

Overdrive Recovery Time, is required for this resumption of

linear operation. The plots of “Unclamped Performance” and

“Clamped Performance” highlight the HS-1135RH’s

2

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