HS-1115RH データシートの表示（PDF） - Intersil
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HS-1115RH Datasheet PDF : 4 Pages
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HS-1115RH
Application Information
Closed Loop Gain Selection
The HS-1115RH features a novel design which allows the
user to select from three closed loop gains, without any
external components. The result is a more flexible product,
fewer part types in inventory, and more efficient use of board
space.
This “buffer” operates in closed loop gains of -1, +1, or +2, and
gain selection is accomplished via connections to the ±inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1 (see next section for layout caveats), while grounding -IN
selects a gain of +2. A gain of -1 is obtained by applying the
input signal to -IN with +IN grounded.
The table below summarizes these connections:
GAIN
(ACL)
-1
+1
+2
CONNECTIONS
+INPUT (PIN 3)
-INPUT (PIN 2)
GND
Input
Input
NC (Floating)
Input
GND
Unity Gain Considerations
Unity gain selection is accomplished by floating the -Input of
the HS-1115RH. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance associ-
ated with attaching the -Input lead to the PCB results in
approximately 3dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
Table 1 lists five alternate methods for configuring the
HS-1115RH as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together, and
applying the input signal to this common node. The amplifier
bandwidth drops from 400MHz to 200MHz, but excellent
gain flatness is the benefit. Another drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
capacitor between the inputs shorts them only at high
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
Another straightforward approach is to add a 620Ω resistor
in series with the positive input. This resistor and the
HS-1115RH input capacitance form a low pass filter which
rolls off the signal bandwidth before gain peaking occurs.
This configuration was employed to obtain the datasheet AC
and transient parameters for a gain of +1.
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resis-
tors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10μF) tantalum in parallel with a small value
(0.1μF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier’s
inverting input. At higher frequencies this capacitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 1.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
RS and CL form a low pass network at the output, thus limit-
ing system bandwidth well below the amplifier bandwidth of
225MHz. By decreasing RS as CLincreases the maximum
bandwidth is obtained without sacrificing stability.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS
APPROACH
PEAKING (dB)
BW (MHz)
+SR/-SR (V/μs)
±0.1dB GAIN FLATNESS
(MHz)
Remove Pin 2
2.5
400
1200/850
20
+RS = 620Ω
0.6
170
1125/800
25
+RS = 620Ω and Remove Pin 2
0
165
1050/775
65
Short Pins 2, 3
0
200
875/550
45
100pF cap. between pins 2, 3
0.2
190
900/550
19
FN4098.1
2
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