A29L160UG-70 データシートの表示（PDF） - AMIC Technology
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A29L160UG-70 Datasheet PDF : 42 Pages
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A29L160 Series
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY / BY pin, or by
reading the I/O7 (Data Polling) and I/O6 (toggle) status bits.
After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L160 is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Pin Configurations
SOP
RESET
1
A18
2
A17
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
11
CE
12
VSS
13
OE
14
I/O0
15
I/O8
16
I/O1
17
I/O9
18
I/O2
19
I/O10
20
I/O3
21
I/O11
22
44
WE
43 A19
42
A8
41
A9
40
A10
39
A11
38 A12
37
A13
36
A14
35
A15
34 A16
33
BYTE
32 VSS
31
I/O15 (A-1)
30
I/O7
29
I/O14
28
I/O6
27
I/O13
26
I/O5
25
I/O12
24
I/O4
23
VCC
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
A19 9
NC 10
WE 11
RESET 12
NC 13
NC 14
RY/BY 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
TSOP (I)
A29L160V
48 A16
47 BYTE
46 VSS
45 I/O15 (A-1)
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 VSS
26 CE
25 A0
(November, 2007, Version 1.2)
2
AMIC Technology, Corp.
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