ISPLS1016EA-100LJ44 データシートの表示（PDF） - Lattice Semiconductor
部品番号
コンポーネント説明
メーカー
ISPLS1016EA-100LJ44 Datasheet PDF : 13 Pages
| |||
Specifications ispLSI 1016EA
Pin Description
NAME
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0/IN 31
PLCC
PIN NUMBERS
15, 16, 17, 18,
19, 20, 21, 22,
25, 26, 27, 28,
29, 30, 31, 32,
37, 38, 39, 40,
41, 42, 43, 44,
3, 4, 5, 6,
7, 8, 9, 10
2
TDI
14
TMS
36
TQFP
PIN NUMBERS
DESCRIPTION
9, 10, 11, 12,
13, 14, 15, 16,
19, 20, 21, 22,
23, 24, 25, 26,
31, 32, 33, 34,
35, 36, 37, 38,
41, 42, 43, 44,
1, 2, 3, 4
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
40
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
8
Input - Functions as an input pin to load programming data into the device and
also used as one of the two control pins for the ispJTAG state machine.
30
Input - Controls the operation of the ISP state machine.
TDO
24
18
Output - Functions as an output pin to read serial shift register data.
TCK
33
27
Input - Functions as a clock pin for the Serial Shift Register.
Y0
11
Y1/RESET1
35
5
Dedicated Clock input. This clock input is connected to one of the clock inputs
of all of the GLBs on the device.
29
This pin performs two functions:
Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB on the device.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the
device.
GND
VCC
1, 23
12, 34
17, 39
6, 28
Ground (GND)
VCC
VCCIO
13
7
Supply voltage for output drivers, 5V or 3.3V.
1. Pins have dual function capability which is software selectable.
Table 2-0002C/1016EA
11
Share Link: 