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ISPLS1016EA-100LT44 データシートの表示(PDF) - Lattice Semiconductor

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ISPLS1016EA-100LT44
Lattice
Lattice Semiconductor Lattice
ISPLS1016EA-100LT44 Datasheet PDF : 13 Pages
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Specifications ispLSI 1016EA
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 4 #2
COND.
DESCRIPTION1
-200
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A
tpd2
A
fmax (Int.) A
fmax (Ext.)
fmax (Tog.)
tsu1
1 Data Propagation Delay, 4PT Bypass, ORP Bypass 4.5 7.5 10.0 ns
2 Data Propagation Delay, Worst Case Path
6.0 10.0 12.5 ns
3 Clock Frequency with Internal Feedback 3
200 125 100 MHz
4
Clock
Frequency
with
External
Feedback
(
1
tsu2 +
) tco1
143
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
twl
)
250
100
167
77
125
MHz
MHz
6 GLB Reg. Setup Time before Clock,4 PT Bypass 3.0 4.5 6.0 ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
3.5 4.5 6.0 ns
th1
8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 0.0 0.0 ns
tsu2
9 GLB Reg. Setup Time before Clock
3.5 5.5 7.0 ns
tco2
10 GLB Reg. Clock to Output Delay
4.0 5.5 7.0 ns
th2
11 GLB Reg. Hold Time after Clock
0.0 0.0 0.0 ns
tr1
A 12 Ext. Reset Pin to Output Delay
5.5 10.0 13.5 ns
trw1
tptoeen
13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
3.5 5.0 6.5 ns
7.0 12.0 15.0 ns
tptoedis
C 15 Input to Output Disable
7.0 12.0 15.0 ns
tgoeen
B 16 Global OE Output Enable
4.5 7.0 9.0 ns
tgoedis
C 17 Global OE Output Disable
4.5 7.0 9.0 ns
twh
18 External Synchronous Clock Pulse Duration, High 2.0 3.0 4.0 ns
twl
19 External Synchronous Clock Pulse Duration, Low 2.0 3.0 4.0 ns
tsu3
20 I/O Reg. Setup Time before Ext. Sync Clock (Y1) 3.0 3.0 3.5 ns
th3
21 I/O Reg. Hold Time after Ext. Sync. Clock (Y1)
0.0 0.0 0.0 ns
1.
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
Table 2-0030A/1016EA
v.2.6
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
6

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