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ISPLS1016EA-200LT44 データシートの表示(PDF) - Lattice Semiconductor

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ISPLS1016EA-200LT44
Lattice
Lattice Semiconductor Lattice
ISPLS1016EA-200LT44 Datasheet PDF : 13 Pages
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Specifications ispLSI 1016EA
Internal Timing Parameters1
PARAM. #2
DESCRIPTION
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
tgrp16 32 GRP Delay, 16 GLB Loads
GLB
t4ptbpc 33 4 ProductTerm Bypass Path Delay (Combinatorial)
t4ptbpr 34 4 Product Term Bypass Path Delay (Registered)
t1ptxor 35 1 ProductTerm/XOR Path Delay
t20ptxor 36 20 Product Term/XOR Path Delay
txoradj 37 XOR Adjacent Path Delay 3
tgbp 38 GLB Register Bypass Delay
tgsu
tgh
39 GLB Register Setup Time before Clock
40 GLB Register Hold Time after Clock
tgco
tgro
tptre
tptoe
tptck
tgfb
41 GLB Register Clock to Output Delay
42 GLB Register Reset to Output Delay
43 GLB Product Term Reset to Register Delay
44 GLB Product Term Output Enable to I/O Cell Delay
45 GLB Product Term Clock Delay
46 GLB Feedback Delay
ORP
torp
torpbp
47 ORP Delay
48 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
-200
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
0.3 0.3 0.4 ns
4.0 4.0 4.0 ns
3.0 3.0 3.4 ns
0.0 0.0 0.0 ns
4.0 4.6 5.0 ns
4.0 4.6 5.0 ns
1.1 1.9 2.2 ns
1.3 1.7 2.1 ns
1.5 1.9 2.3 ns
1.7 2.1 2.5 ns
2.1 2.5 2.9 ns
1.7 3.4 4.9 ns
1.8 3.1 4.9 ns
1.9 3.6 4.3 ns
1.9 3.6 4.3 ns
1.9 3.6 4.3 ns
0.6 1.2 2.1 ns
0.2 0.3 0.3 ns
1.0 3.5 4.0 ns
1.4 1.4 1.7 ns
3.8 4.9 5.0 ns
2.5 3.8 4.5 ns
2.1 5.7 7.2 ns
1.5 2.5 2.8 3.9 3.5 4.7 ns
0.0 0.3 0.3 ns
0.8
0.1
1.3
0.2
1.4 ns
0.4 ns
Table 2-0036A/1016EA
v.2.6
7

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