ISPLS1016EA-100LJ44 データシートの表示（PDF） - Lattice Semiconductor

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ISPLS1016EA-100LJ44

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1016EA

Internal Timing Parameters1

PARAM. #

DESCRIPTION

Outputs

tob

49 Output Buffer Delay

tsl

50 Output Buffer Delay, Slew Limited Adder

toen

51 I/O Cell OE to Output Enabled

todis

tgoe

52 I/O Cell OE to Output Disabled

53 Global OE

Clocks

tgy0

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk)

tgy1

55 Clock Delay, Y1 to Global GLB Clock Line

tgcp

tioy1

56 Clock Delay, Clock GLB to Global GLB Clock Line

57 Clock Delay, Y1 to I/O Cell Global Clock Line

tiocp

58 Clock Delay, Clock GLB to I/O Cell Global Clock Line

Global Reset

tgr

59 Global Reset to GLB and I/O Registers

1. Internal Timing Parameters are not tested and are for reference only.

-200

-125

-100

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

— 0.9 — 1.7 — 2.0 ns

— 5.0 — 5.0 — 5.0 ns

— 3.1 — 4.0 — 5.1 ns

— 3.1 — 4.0 — 5.1 ns

— 1.4 — 3.0 — 3.9 ns

0.9 0.9 1.1 1.1 1.9 1.9 ns

0.9 0.9 0.9 0.9 1.5 1.5 ns

0.8 1.8 0.8 1.8 0.8 1.8 ns

0.0 0.0 0.0 0.0 0.0 0.0 ns

0.8 2.8 0.8 2.8 0.8 2.8 ns

— 0.0

— 2.1

— 5.1 ns

Table 2-0037A/1016EA

v.2.6

8

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