ISPLS1016EA-200LT44 データシートの表示（PDF） - Lattice Semiconductor

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ISPLS1016EA-200LT44

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1016EA

ispLSI 1016EA Timing Model

I/O Cell

GRP

GLB

Ded. In

I/O Pin

(Input)

#59

#28

I/O Reg Bypass

#22

Input

D Register Q

RST

#23 - 27

Reset

GRP4

#30

GRP Loading

Delay

#29, 31 - 32

#46

Feedback

#33 Comb 4 PT Bypass

Reg 4 PT Bypass

#34

20 PT

XOR Delays

#35 - 37

#59

GLB Reg Bypass

#38

GLB Reg

Delay

D

Q

RST

#39 - 42

ORP

I/O Cell

ORP Bypass

#48

ORP

Delay

#47

#49, 50

I/O Pin

(Output)

#51, 52

Clock

Distribution

Control RE

PTs OE

Y1

#55 - 58

#43 - 45 CK

#54

Y0

GOE 0

#53

Derivations of tsu, th and tco from the Product Term Clock1

tsu

= Logic + Reg su - Clock (min)

= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))

= (#22 + #30 + #36) + (#39) - (#22 + #30 + #45)

0.9 = (0.3 + 1.5 + 1.9) + (0.2) - (0.3 + 1.5 + 1.2)

th

= Clock (max) + Reg h - Logic

= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

= (#22 + #30 + #45) + (#40) - (#22 + #30 + #36)

1.6 = (0.3 + 1.5 + 2.5) + (1.0) - (0.3 + 1.5 + 1.9)

tco

= Clock (max) + Reg co + Output

= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)

= (#22 + #30 + #45) + (#41) + (#47 + #49)

7.2 = (0.3 + 1.5 + 2.5) + (1.4) + (0.8 + 0.9)

Derivations of tsu, th and tco from the Clock GLB 1

tsu

= Logic + Reg (setup) - Clock (min)

= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))

= (#22 + #30 + #36) + (#39) - (#54 + #41 + #56)

1.1 = (0.3 + 1.5 + 1.9) + (0.2) - (0.9 + 1.4 + 0.8)

th

= Clock (max) + Reg (hold) - Logic

= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

= (#54 + #41 + #56) + (#40) - (#22 + #30 + #36)

1.4 = (0.9 + 1.4 + 1.8) + (1.0) - (0.3 + 1.5 + 1.9)

tco

= Clock (max) + Reg (clock-to-out) + Output

= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

= (#54 + #41 + #56) + (#41) + (#47 + #49)

7.2 = (0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9)

1. Calculations are based upon timing specifications for the ispLSI 1016EA-200.

Table 2-0042a/1016EA

v.2.6

0491/1016EA

9

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