RIVA128 データシートの表示（PDF） - STMicroelectronics

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RIVA128

RIVA 128™ 128-BIT 3D MULTIMEDIA ACCELERATOR

STMicroelectronics 

RIVA 128

128-BIT 3D MULTIMEDIA ACCELERATOR

TABLE OF CONTENTS

1 REVISION HISTORY ...................................................................................................................... 4

1 RIVA 128 300PBGA DEVICE PINOUT .......................................................................................... 5

2 PIN DESCRIPTIONS ...................................................................................................................... 6

2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ..................................................... 6

2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................ 6

2.3 SGRAM FRAMEBUFFER INTERFACE ................................................................................ 8

2.4 VIDEO PORT......................................................................................................................... 8

2.5 DEVICE ENABLE SIGNALS.................................................................................................. 9

2.6 DISPLAY INTERFACE .......................................................................................................... 9

2.7 VIDEO DAC AND PLL ANALOG SIGNALS .......................................................................... 9

2.8 POWER SUPPLY .................................................................................................................. 9

2.9 TEST...................................................................................................................................... 10

3 OVERVIEW OF THE RIVA 128 ...................................................................................................... 11

3.1 BALANCED PC SYSTEM...................................................................................................... 11

3.2 HOST INTERFACE ............................................................................................................... 11

3.3 2D ACCELERATION ............................................................................................................. 12

3.4 3D ENGINE ........................................................................................................................... 12

3.5 VIDEO PROCESSOR............................................................................................................ 12

3.6 VIDEO PORT......................................................................................................................... 13

3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER ......................................... 13

3.8 SUPPORT FOR STANDARDS.............................................................................................. 13

3.9 RESOLUTIONS SUPPORTED.............................................................................................. 13

3.10 CUSTOMER EVALUATION KIT............................................................................................ 14

3.11 TURNKEY MANUFACTURING PACKAGE........................................................................... 14

4 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ............................................................. 15

4.1 RIVA 128 AGP INTERFACE ................................................................................................. 16

4.2 AGP BUS TRANSACTIONS.................................................................................................. 16

5 PCI 2.1 LOCAL BUS INTERFACE................................................................................................. 22

5.1 RIVA 128 PCI INTERFACE ................................................................................................... 22

5.2 PCI TIMING SPECIFICATION............................................................................................... 23

6 SGRAM FRAMEBUFFER INTERFACE......................................................................................... 29

6.1 SGRAM INITIALIZATION ...................................................................................................... 31

6.2 SGRAM MODE REGISTER .................................................................................................. 31

6.3 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................ 32

6.4 SGRAM INTERFACE TIMING SPECIFICATION .................................................................. 32

7 VIDEO PLAYBACK ARCHITECTURE........................................................................................... 37

7.1 VIDEO SCALER PIPELINE ................................................................................................... 38

8 VIDEO PORT .................................................................................................................................. 40

8.1 VIDEO INTERFACE PORT FEATURES ............................................................................... 40

8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC .............................. 41

8.3 TIMING DIAGRAMS .............................................................................................................. 42

8.4 656 MASTER MODE ............................................................................................................. 46

8.5 VBI HANDLING IN THE VIDEO PORT ................................................................................. 47

8.6 SCALING IN THE VIDEO PORT ........................................................................................... 47

9 BOOT ROM INTERFACE............................................................................................................... 48

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