MXED202 データシートの表示（PDF） - Clare Inc => IXYS
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MXED202 Datasheet PDF : 16 Pages
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Preliminary
Chip Supply Currents - Exclusive of Load
Parameter
Logic Supply,
Operating
Logic Supply,
Powerdown
High Voltage
Supply, Operating
High Voltage Supply,
Powerdown
Sym
IVCC
IVCC
IVMAX
IVMAX
Operating Condition
VDRV>1V, fCLK<100kHz
3V<VCC<5.5V
VDRV<0.3V, 3V<VCC<5.5V
VDRV>1V, fCLK<100kHz
9V<MAX<30V
VDRV<0.3V, 9V<MAX<30V
MXED202
Min
Typ Max Units
-
140 210
µA
-
15
25
µA
-
445 700
µA
-
-
20
µA
Digital Inputs: SHR, SRIN, SLIN, DUAL, CLK, PCB, MONO, S128, RSTB
Parameter
Input low voltage
Input high voltage
Input current
Clock Rise Time
Clock Fall Time
Clock Duty Cycle
Setup Time
Hold Time
Sym
VIL
VIH
II
CLKRT
CLKFT
CLK%
TSet
THold
Operating Condition
Min
Typ
-
-
-
-
VCC-0.4 -
-
-10
-
-
-
-
-
-
-
20
-
Time in advance of 10% rising edge 50
-
of CLK that inputs SHR, SRIN, SLIN,
DUAL, PCB, MONO, S128, CLRB
must be at valid input logic levels
to take effect on next clock cycle.
Time subsequent to 90% rising edge 50
-
of CLK that inputs SHR, SRIN, SLIN,
DUAL, PCB, MONO, S128, CLRB
must be valid to take effect on next
rising edge of the clock (CLK).
Digital Outputs: SRIN, SLIN, ROPT
Parameter
Output low voltage
Output high voltage
Output rise/fall time
Precharge Timing
Resistor connected
to pin ROPT
Sym
VOL
VOH
TRF
RROPT
Operating Condition
Iout = 200 µA
Iout = -200 µA
10 to 90 %, Cload = 5 pF
Pages 9-11
Min
Typ
-
-
VCC-0.4
-
-
-
50
-
Max
0.4
-
10
5
5
80
-
-
Max
0.4
-
5
200
Units
V
V
µA
nS
nS
%
nS
nS
Units
V
V
nS
kΩ
Rev. 2
www.clare.com
7
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