MCM63F733ATQ10R データシートの表示（PDF） - Motorola => Freescale
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MCM63F733ATQ10R Datasheet PDF : 16 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 through 4)
MCM63F733A–10
75 MHz
MCM63F733A–11
66 MHz
Parameter
Symbol
Min
Max
Min
Max
Unit Notes
Cycle Time
tKHKH
13
—
15
—
ns
Clock High Pulse Width
tKHKL
5.2
—
6
—
ns
Clock Low Pulse Width
tKLKH
5.2
—
6
—
ns
Clock Access Time
tKHQV
—
10
—
11
ns
Output Enable to Output Valid
tGLQV
—
3.8
—
3.8
ns
Clock High to Output Active
tKHQX1
0
—
0
—
ns
5, 6
Clock High to Output Change
tKHQX2
1.5
—
1.5
—
ns
6
Output Enable to Output Active
tGLQX
0
—
0
—
ns
5, 6
Output Disable to Q High–Z
tGHQZ
—
3.8
—
3.8
ns
5, 6
Clock High to Q High–Z
tKHQZ
1.5
3.8
1.5
3.8
ns
5, 6
Setup Times:
Address
tADKH
2
—
2
—
ns
ADSP, ADSC, ADV tADSKH
Data In
tDVKH
Write
tWVKH
Chip Enable
tEVKH
Hold Times:
Address
tKHAX
0.5
—
0.5
—
ns
ADSP, ADSC, ADV tKHADSX
Data In
tKHDX
Write
tKHWX
Chip Enable
tKHEX
Sleep Mode Standby
tZZS
—
2x
—
2x
ns
tKHKH
tKHKH
Sleep Mode Recovery
tZZREC
2x
—
2x
—
ns
tKHKH
tKHKH
Sleep Mode High to Q High–Z
tZZQZ
—
15
—
15
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
5. This parameter is sampled and not 100% tested.
6. Measured at ± 200 mV from steady state.
MOTOROLA FAST SRAM
MCM63F733A
9
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