STA001 データシートの表示（PDF） - STMicroelectronics

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STA001

RF FRONT-END FOR DIGITAL RADIO

STMicroelectronics 

STA001

Data Validity

The data on the SDA line must be stable during the high period of the clock. The HIGH to LOW state of the data

line can only change when the clock signal on the SCL line is LOW.

Start and Stop conditions

A start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW

to HIGH transition of the SDA line while SCL is HIGH.

Byte format

Every byte transferred on the SDA line must contains bits. Each byte must be followed by an acknowledge bit.

The MSB is transferred first.

Acknowledge

The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse. The peripheral

(STA001) that acknowledges has to pull-down (LOW) the SDA line during the clock pulse.

The STA001 which has been addressed has to generate an acknowledge after the reception of each byte, oth-

erwise the SDA line remains at at the HIGH level during the ninth clock pulse time. In this case the µP can gen-

erate the STOP information in order to abort the transfer.

Transmission without acknwoledge

Avoiding to detect the acknowlegde of the STA001, the µP can use a simpler transmission: simply it waits one

clock period without checking the STA001 acknowledging, and sends the new data.

This approach of course is less protected from misworking.

Figure 2. Validity on the I2CBUS

SDA

SCL

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

D99AU1031

Figure 3. Timing Diagram of the I2CBUS

SCL

SDA

START

D99AU1032

I2CBUS

STOP

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