AD725 データシートの表示（PDF） - Analog Devices
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AD725 Datasheet PDF : 20 Pages
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AD725
PIN DESCRIPTIONS
Pin Mnemonic Description
Equivalent Circuit
1 STND
2 AGND
3 4FSC
4 APOS
5 CE
6 RIN
7 GIN
8 BIN
9 CRMA
10 COMP
11 LUMA
12 YTRAP
13 DGND
14 DPOS
15 VSYNC
16 HSYNC
Encoding Standard Pin. A Logic HIGH input selects NTSC encoding.
A Logic LOW input selects PAL encoding.
TTL Logic Levels.
Analog Ground Connection.
4FSC Clock Input.
For NTSC: 14.318 180 MHz.
For PAL: 17.734 475 MHz.
TTL Logic Levels.
Analog Positive Supply (+5 V ± 5%).
Chip Enable. A Logic HIGH input enables the encode function.
A Logic LOW input powers down chip when not in use.
TTL Logic Levels.
Red Component Video Input.
0 mV to 714 mV AC-Coupled.
Green Component Video Input.
0 mV to 714 mV AC-Coupled.
Blue Component Video Input.
0 mV to 714 mV AC-Coupled.
Chrominance Output.*
Approximately 1.8 V peak-to-peak for both NTSC and PAL.
Composite Video Output.*
Approximately 2.5 V peak-to-peak for both NTSC and PAL.
Luminance plus CSYNC Output.*
Approximately 2 V peak-to-peak for both NTSC and PAL.
Luminance Trap Filter Tap. Attach L-C resonant network to reduce cross-color artifacts.
Digital Ground Connection.
Digital Positive Supply (+5 V ± 5%).
Vertical Sync Signal (if using external CSYNC set at > +2 V). TTL Logic Levels.
Horizontal Sync Signal (or CSYNC signal). TTL Logic Levels.
Circuit A
Circuit A
Circuit A
Circuit B
Circuit B
Circuit B
Circuit C
Circuit C
Circuit C
Circuit D
Circuit A
Circuit A
*The Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75 Ω reverse-terminated lines.
DPOS
1
3
5
15 DGND
16
DPOS
6
7
8
DGND
VCLAMP
APOS DPOS
9
10
11
AGND DGND
APOS
DPOS
1k⍀
12
AGND
DGND
Circuit A
Circuit B
Circuit C
Figure 1. Equivalent Circuits
Circuit D
–4–
REV. 0
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