IDT79R3500 データシートの表示（PDF） - Integrated Device Technology

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IDT79R3500

RISC CPU PROCESSOR RISCore™

Integrated Device Technology 

IDT79R3500 RISC CPU PROCESSOR RISCore

MILITARY AND COMMERCIAL TEMPERATURE RANGES

• External Cache Memory—Local, high-speed memory

(called cache memory) is used to hold instructions and

data that is repetitively accessed by the CPU (for example,

within a program loop) and thus reduces the number of

references that must be made to the slower-speed main

memory. Some microprocessors provide a limited amount

of cache memory on the CPU chip itself. The external

caches supported by the IDT79R3500 can be much larger;

while a small cache can improve performance of some

programs, significant improvements for a wide range of

programs require large caches.

• Separate Caches for data and Instructions—Even with

high-speed caches, memory speed can still be a limiting

factor because of the fast cycle time of a high-performance

microprocessor. The IDT79R3500 supports separate

caches for instructions and data and alternates accesses

of the two caches during each CPU cycle. Thus, the

processor can obtain data and instructions at the cycle rate

of the CPU using caches constructed with commercially

available IDT static RAM devices.

In order to maximize bandwidth in the cache while minimiz-

ing the requirement for SRAM access speed, the

IDT79RR3500 divides a single-processor clock cycle into

two phases. During one phase, the address for the data

cache access is presented while data previously ad-

dressed in the instruction cache is read; during the next

phase, the data operation is completed while the instruc-

tion cache is being addressed. Thus, both caches are read

in a single processor cycle using only one set of address

and data pins.

• Write Buffer—in order to ensure data consistency, all data

that is written to the data cache must also be written out to

main memory. The cache write model used by the

IDT79R3500 is that of a write-through cache; that is, all

data written by the CPU is immediately written into the

main memory. To relieve the CPU of this responsibility

(and the inherent performance burden) the IDT79R3500

supports an interface to a write buffer. The IDT79R3020

Write Buffer captures data (and associated addresses)

output by the CPU and ensures that the data is passed on

to main memory.

IDT79R3500 Processor Subsystem Interfaces

Figure 14 illustrates the three subsystem interfaces pro-

vided by the IDT79R3500 processor:

• Cache control interface (on-chip) for separate data and

instruction caches permits implementation of off-chip

caches using standard IDT SRAM devices. The

IDT79R3500 directly controls the cache memory with a

minimum of external components. Both the instruction and

data cache can vary from 0 to 256kB (64K entries). The

IDT79R3500 also includes the TAG control logic which

determines whether or not the entry read from the cache

is the desired data. The IDT79RR3500 implements an

advanced feature that allows certain tag comparisons to

be eliminated, which in turn reduces the number of cache

SRAMs required. The Int(5) reset mode vector contains

two bits which sets the tag comparison options. Table 3

illustrates the tag disable encoding. The first row in the

table implements the standard IDT79R3000A operating

mode where all the tag and tag parity are used. The

second row eliminates the upper 4 tag bits, eliminating

normally required SRAMs and limiting main memory ad-

dressing to 128mB. The third row elimnates the lower 4 tag

bits, which requires the cache to be at least 64kB each.

The fourth row eliminates the upper 4 and lower 4 tag bits,

requiring at least 16K cache entries, and limits main

memory addressing to 128mB. In all cases, the IDT79R3500

continues to check tag parity which are selected as driven

from the cache. The IDT79R3500 cache controller imple-

ments a direct mapped cache for high net performance

(bandwidth). It has the ability to refill multiple words when

a cache miss occurs, thus reducing the effective miss rate

to less than 2% for large caches. When a cache miss

occurs, the IDT79R3500 can support refilling the cache in

1, 4, 8, 16, or 32 word blocks to minimize the effective

penalty of having to access main memory. The IDT79R3500

also incorporates the ability to perform instruction stream-

ing; while the cache is refilling, the processor can resume

execution once the missed word is obtained from main

memory. In this way, the processor can continue to execute

concurrently with the cache block refill.

• Memory controller interface for system (main) memory.

This interface also includes the logic and signals to allow

operation with a write buffer to further improve memory

bandwidth. In addition to the standard full word access, the

memory controller supports the ability to write bytes and

half-words by using partial word operations. The memory

controller also supports the ability to retry memory ac-

cesses if, for example, the data returned from memory is

invalid and a bus error needs to be signalled.

• Coprocessor Interface—The IDT79R3500 features a set

of on board tightly coupled coprocessors. Coprocessor 0

is defined to be the system control coprocessor and

Coprocessor 1 is the Floating Point Accelerator. They

have direct access to the internal data bus which allows

them direct load and store of data in the same fashion as

accessing the CPU registers. This relieves the typical

bottleneck of having to load data into the CPU register set

and then passing that data off to the co-processors.

In applications where the FPA was off chip, as in using the

IDT79R3010A, several control pins were used for commu-

nications with the CPU and a Phase Lock Loop was

located on the IDT79R3010A to synchronize the two

together. As they are now integrated into a single chip,

these are no longer needed. The FpCond output, which is

used in coprocessor branch instructions, is now internally

tied to the CpCond(1) input of the CPU leaving the external

CpCond(1) pin available for another function. This signal

is selectable to either output the FpBusy or the Fplnt. Cp

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