TDA8083H データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

TDA8083H

Satellite Demodulator and Decoder (SDD3)

Philips Electronics 

Philips Semiconductors

Satellite Demodulator and Decoder

(SDD3)

Product specification

TDA8083

GENERAL DESCRIPTION

This document specifies a DVB compliant demodulator

and forward error correction decoder IC for reception of

QPSK or BPSK modulated signals for satellite

applications. The Satellite Demodulator and Decoder

(SSD) can handle variable symbol rates without adapting

the analog filters within the tuner. Typical applications for

this device are:

• MCPC (Multi-Channel Per Carrier): one QPSK or

BPSK modulated signal in a single satellite channel

(transponder)

• Simul-cast: QPSK or BPSK modulated signal together

with a Frequency Modulated (FM) signal in a single

satellite channel (transponder).

The TDA8083 can handle variable symbol rates in the

range of 12 to 30 Msymbols/s with a minimum number of

low cost and non-critical external components.

The TDA8083 has minimal interfaces with the tuner. It only

requires the demodulated analog I and Q baseband input

signals and provides a tuner AGC control signal.

Analog-to-digital conversion is done internally by two

matched 7-bit ADCs.

The TDA8083 runs on a low frequency crystal which is

upconverted to a clock frequency by means of an internal

PLL. Furthermore, the TDA8083 has an internal anti-alias

filter, which can cover the range of symbol frequencies

without the need to switch external (SAW) filters.

The TDA8083 has a double carrier loop configuration

which has excellent capabilities of tracking phase noise.

Synchronization of the FEC unit is done completely

internally, thereby minimizing I2C-bus communication.

The output of the TDA8083 allows different output modes

(parallel or serial) to interface to a demultiplexer,

descrambler or MPEG-2 decoder including a 3-state

mode. For evaluation of the TDA8083, demodulator and

Viterbi decoder outputs can be made available externally.

The SDD can be controlled and monitored by the I2C-bus.

A 5-bit bidirectional I/O expander and an interrupt line are

available. By sending an interrupt signal, the SDD can

inform the microcontroller of its internal status. Separate

resets are available for logic only, logic plus the I2C-bus

and carrier loops. A switchable I2C-bus loop-through to the

tuner is implemented to switch off the I2C-bus connection

to the tuner. This reduces phase noise in the tuner in case

of I2C-bus crosstalk.

Furthermore, for dish control applications hardware

supports DiSEqC 1.X and tone burst generation via

I2C-bus control. A 22 or a 44 kHz carrier can be generated

(tone mode).

1999 Jul 28

3

Share Link: