YTD423(1999) データシートの表示（PDF） - Yamaha Corporation

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YTD423
(Rev.:1999)

ISDN BRI controller with B-ch HDLC controllers

Yamaha Corporation 

4.3 DC Characteristics

(VDD = 5 V 6 5%, Top = 020 - 70 C)

Parameter

Symbol Condition

Min. Typ. Max. Units

High-Level Input Voltage (CMOS) VIH

(Note 1) 0.8VDD

V

Low-Level Input Voltage (CMOS)

VIL

(Note 1)

0.2VDD V

High-Level Input Voltage (TTL)

VIH

(Note 2) 2.2

V

Low-Level Input Voltage (TTL)

High-Level Output Voltage (CMOS)

Low-Level Output Voltage (CMOS)

VIL

VOH

VOL

(Note 2)

jjIIOOHLjj

<

<

10A

10A

VDD00:4

0.8 V

V

VSS+0.4 V

High-Level Output Voltage (TTL) VOH

(Note 3) 2.7

V

Low-Level Output Voltage (TTL) VOL

(Note 3)

0.4 V

Low-Level Output Voltage (Open-D) VOL

Leakage Current

O-State Leakage Current

IILLZ

(Note 4)

010

(Note 5) 010

0.4 V

10 A

10 A

Power Supply Current

IDD

(Note 6)

17

mA

(Note 7)

0.2

mA

Note 1: With respect to X1,RESET, TEST1, TEST2, WAKEUP, PDET, CLKSEL, PSDET pins.

Note 2: With respect to other pins.

Note 3: CLKOUT pin Test condition: IOH = -1.0 mA, IOL = 2.0 mA

other output pins Test condition: IOH = -0.4 mA, IOL = 1.2 mA

Note 4: HTD, LTD, INT pin Test condition : IOL = 1.2 mA

INF1 pin

Test condition : IOL = 3 mA

RBHW pin

Test condition : IOL = 0.8 mA, RL = 500

Note 5: With respect to cases in which D0-D15, A0-A23, and UBE pins are in the input state and

MWR and MRD pins are in Hi-Z state.

Note 6: RUN state (SYSCLK = 8 MHz)

Note 7: SLEEP state

9

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