YTD423-S データシートの表示（PDF） - Yamaha Corporation

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YTD423-S

ISDN BRI controller with B-ch HDLC controllers

Yamaha Corporation 

YTD423

IHDLC2

ISDN BRI controller with B-ch HDLC controllers

1 INTRODUCTION

YTD423 is a high-performance communication LSI for the ISDN BRI user-network interface function (digital

four-wire time-division full-duplex operation), supporting D-channel layer 1, layer 2 and HDLC controller for B-

channels, all in one 100-pin SQFP chip. YTD423 supports layer 1 (physical layer) control function conforming

to ITU-T Recommendation I.430 and fully supports layer 2 (LAP-D protocol) function conforming to ITU-T

Recommendations Q.920 and Q.921. ETSI (European Telecommunications Standards Institute) and several North

American standard operating modes are also supported. In addition, YTD423 includes layer 3 processor interface

function and 2-channel HDLC controller for B-channels, which operate in DMA transfer mode or I/O transfer

mode. This gives a great advantage to mounting and functional designing of both \active" (with CPU on board)

terminal equipment and \passive" (no CPU on board) PC cards. In order to support the U interface, YTD423 has

a TTL interface (no built-in analog driver/receiver) suitable for connecting to an NT1 chip or a DSU module. S/T

reference point can also be supported by connecting it to YTD421 (analog driver/receiver LSI).

1.1 Features

1. Layer 1 function

 Supports layer 1 control function conforming to ITU-T Recommendation I.430 [1992 edition] and TTC

Standard JT-I430 [1993 edition] (default)

{ TTL interface

{ 192 kbps transmission rate

{ Interface structure : 2B + D (B = 64 kbps, D = 16 kbps)

{ Frame assembling and disassembling function

{ Collision control (built-in random number (Ri) reset), priority control (built-in retransmission con-

trol), and state transition control

{ Programmable T3 and T4 timers

YTD423D CATALOG

CATALOG No.:4TD423D2

2001.1

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