OQ2541HP/C2 データシートの表示（PDF） - Philips Electronics

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OQ2541HP/C2

SDH/SONET data and clock recovery unit STM1/4/16 OC3/12/48 GE

Philips Electronics 

Philips Semiconductors

SDH/SONET data and clock recovery unit

STM1/4/16 OC3/12/48 GE

Product specification

OQ2541HP; OQ2541U

External capacitor for loop filter

The loop filter is an integrator with a built-in capacitance of

2 × 130 pF. An external capacitance of 200 nF must be

connected between pins CAPUPQ and CAPDOQ to

ensure loop stability while the frequency window detector

is active.

Loop mode enable

The loop mode is provided for system testing (see Fig.8).

The loop mode is enabled by applying a voltage lower than

0.8 V (TTL LOW-level) to pin ENL. This selects the loop

mode: the outputs on pins DLOOP, DLOOPQ, CLOOP

and CLOOPQ are switched on.

If a voltage higher than 2.0 V (TTL HIGH-level) is applied

to pin ENL, then pins DOUT, DOUTQ, COUT and COUTQ

are switched on while pins DLOOP, DLOOPQ, CLOOP

and CLOOPQ are disabled to minimize power

consumption.

If pin ENL is connected to VEE (−3.3 V), all outputs are

enabled.

handboook,ffhcalhfpipage

ENL

on chip

36 kΩ

GND

VEE

DECODER

LOGIC

MGL668

Fig.8 Input circuit of pin ENL.

Lock detection

Pin LOCK should be interpreted as an indication for the

presence of the reference clock on pin CREF and for

properly functioning of the acquisition aid (frequency

window detector).

Pin LOCK is an open-collector TTL output and should be

pulled up with a 10 kΩ resistor to a positive supply voltage.

If the VCO frequency is within a 1000 ppm window around

the desired frequency, pin LOCK will remain at a

HIGH-level. If no reference clock is present, or the VCO is

outside the 1000 ppm window, pin LOCK will be at a

LOW-level. The logic level on pin LOCK does not indicate

locking of the PLL to the incoming data; this is indicated by

the signal on pin LOS.

Loss of signal detection

The Loss Of Signal (LOS) function is closely related to the

functionality of the Alexander phase detector; see Fig.3 for

the meaning of A, B and T in this section.

In the functional description it is described that the phase

detector does not take any action if the value at sample

points A and B are the same, because there has not been

any transition. However, if levels A and B are the same but

different from level T, this still means there has not been

any transition, but level T has got the wrong level

somehow. This is probably due to noise or bad signal

integrity, which will lead to a bit error. Hence the

occurrence of this particular situation is an indication for bit

errors. If too many of these bit errors occur per time and

the PLL is gradually losing lock, the LOS alarm is asserted.

The LOS alarm assert level is around a Bit Error Rate

(BER) for BER = 5 ⋅ 10−2 and the de-assert level is around

BER = 1 ⋅ 10−3.

The LOS function will only work properly if the input signal

is larger than the input offset of the OQ2541; otherwise,

the signal will be masked by the input offset and

interpreted as consecutive bits of the same sign, thus

obstructing a proper LOS detection. In practice an optical

front-end device with a noise level (RMS value) larger than

the specified offset of the OQ2541 will ensure a proper

LOS indication.

The LOS detection is BER related, but neither dependent

on the data stream content, nor protocol. Therefore, an

SDH/SONET data stream is no prerequisite for a proper

LOS function. Since the LOS function of the OQ2541 is

derived from digital signals, it is a good supplement to an

analog, amplitude based, LOS indication.

Pin LOS is an open-collector TTL compatible output.

A pull-up resistor should be connected to a positive supply

voltage.

Pin LOS will be at a HIGH-level (TTL) if the data signal is

absent on pins DIN and DINQ or if BER > 5 ⋅ 10−2;

otherwise pin LOS will be at a LOW-level if BER < 1 ⋅ 10−3.

1999 May 27

9

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