TZA3034T データシートの表示（PDF） - Philips Electronics

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TZA3034T

SDH/SONET STM1/OC3 postamplifier

Philips Electronics 

Philips Semiconductors

SDH/SONET STM1/OC3 postamplifier

Product specification

TZA3034

FUNCTIONAL DESCRIPTION

The TZA3034 accepts up to 155 Mbits/s SDH/SONET

data streams, with amplitudes from 2 mV up to 1.5 V (p-p)

single-ended. The input signal will be amplified and limited

to differential PECL output levels (see Fig.1).

The input buffer A1 presents an impedance of

approximately 4.5 kΩ to the data stream on the inputs

pin DIN and pin DINQ. The input can be used both

single-ended and differential, but differential operation is

preferred for better performance.

Because of the high gain of the postamplifier, a very small

offset voltage would shift the decision level in such a way

that the input sensitivity decreases drastically. Therefore a

DC offset compensation circuit is implemented in the

TZA3034, which keeps the input of buffer A3 at its toggle

point in the absence of any input signal.

An input signal level detection is implemented to check if

the input signal is above the user-programmed level.

The outcome of this test is available at the PECL outputs,

pins ST and STQ. This flag can also be used to prevent

the PECL outputs pins DOUT and DOUTQ from reacting

to noise in the absence of a valid input signal, by

connecting pin STQ to pin JAM. This guarantees that data

will only be transmitted when the input signal-to-noise ratio

is sufficient for low bit error rate system operation.

PECL logic

The logic level symbol definitions for PECL are shown in

Fig.4.

Input biasing

The inputs, pins DIN and DINQ, are DC biased at

approximately 2.1 V by an internal reference generator

(see Fig.5). The TZA3034 can be DC coupled, but

AC coupling is preferred. In case of DC coupling, the

driving source must operate within the allowable input

signal range (1.3 V to VCCA). Also a DC offset voltage of

more than a few millivolts should be avoided, since the

internal DC offset compensation circuit has a limited

correction range.

If AC coupling is used to remove any DC compatibility

requirement, the coupling capacitors must be large

enough to pass the lowest input frequency of interest.

For example, 1 nF coupling capacitors react with the

internal 4.5 kΩ input bias resistors to yield a lower −3 dB

frequency of 35 kHz. This then sets a limit on the

maximum number of consecutive pulses that can be

sensed accurately at the system data rate. Capacitor

tolerance and resistor variation must be included for an

accurate calculation.

DC-offset compensation

A control loop connected between the inputs of buffer A3

and amplifier A1 (see Fig.1) will keep the input of buffer A3

at its toggle point in the absence of any input signal.

Because of the active offset compensation which is

integrated in the TZA3034, no external capacitor is

required. The loop time constant determines the lower

cut-off frequency of the amplifier chain, which is set at

approximately 850 Hz.

Input signal level detection

The TZA3034 allows for user-programmable input signal

level detection and can automatically disable the switching

of the PECL outputs if the input signal is below a set

threshold. This prevents the outputs from reacting to noise

in the absence of a valid input signal, and insures that data

will only be transmitted when the signal-to-noise ratio of

the input signal is sufficient for low bit-error-rate system

operation. Complementary PECL flags (pins ST and STQ)

indicate whether the input signal is above or below the

programmed threshold level.

The input signal is amplified and rectified before being

compared to a programmable threshold reference. A filter

is included to prevent noise spikes from triggering the level

detector. This filter has a nominal 1 µs time constant and

additional filtering can be achieved by using an external

capacitor between VCCA and pin CF (the internal driving

impedance nominally is 25 kΩ). The resultant signal is

then compared to a threshold current through pin RSET.

This current can be set by connecting an external resistor

between VCCA and pin RSET, or by forcing a current into

pin RSET (see Fig.6).

1999 Nov 03

5

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