CXD3504R データシートの表示（PDF） - Sony Semiconductor

部品番号

コンポーネント説明

メーカー

CXD3504R

Selective Delay Line for LCD

Sony Semiconductor 

Pin Description

Pin

No.

Symbol

I/O

Description

1 VSS

2 PECLCK

P GND

I Very little amp. clock input∗1

3 NC

4 CMOSCK

I CMOS clock input∗2

5 VSS

P GND

6 CLKSEL

I 0: PECL, 1: CMOS

7 SELRA

I SELA (Data path selection A) for R

8 SELGA

I SELA (Data path selection A) for G

9 SELBA

I SELA (Data path selection A) for B

10 SELB

I Data path selection B

11 XCLR

I 0: Direct Reset

12 HD

I Horizontal sync signal input

13 HDSEL

I HD selection (0: ↓, 1: ↑)

14 HDEDGE

I CK trigger selection of HD (0: ↓, 1: ↑)

15 NC

Reserve

16 REDGE

I CK trigger selection of R (0: ↓, 1: ↑)

17 GEDGE

I CK trigger selection of G (0: ↓, 1: ↑)

18 BEDGE

I CK trigger selection of B (0: ↓, 1: ↑)

19 POLSLA

I SELA polarity selection

20 NC

21 NC

22 VDD

P Power supply

23 VSS

P GND

24 B2OUT0

O B2 output

25 B2OUT1

O B2 output

26 B2OUT2

O B2 output

27 B2OUT3

O B2 output

28 B2OUT4

O B2 output

29 VDD

P Power Supply

30 VSS

P GND

31 B2OUT5

O B2 output

32 B2OUT6

O B2 output

33 B2OUT7

O B2 output

∗1 Connect to GND or VDD when using CMOS clock.

∗2 Connect to GND or VDD when using small amplitude clock.

–4–

CXD3504R

Input pin for

open status

L

L

L

L

L

H

L

L

L

L

L

L

Share Link: