AD420AN-32(1999) データシートの表示（PDF） - Analog Devices

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AD420AN-32
(Rev.:1999)

Serial Input 16-Bit 4 mA–20 mA, 0 mA–20 mA DAC

Analog Devices 

AD420

THEORY OF OPERATION

The AD420 uses a sigma-delta (Σ∆) architecture to carry out

the digital-to-analog conversion. This architecture is particularly

well suited for the relatively low bandwidth requirements of the

industrial control environment because of its inherent monoto-

nicity at high resolution.

In the AD420 a second order modulator is used to keep com-

plexity and die size to a minimum. The single bit stream from

the modulator controls a switched current source that is then

filtered by two, continuous time resistor-capacitor sections. The

capacitors are the only external components that have to be

added for standard current-out operation. The filtered current is

amplified and mirrored to the supply rail so that the application

simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA

current source output with respect to ground. The AD420 is

manufactured on a BiCMOS process that is well suited to imple-

menting low voltage digital logic with high performance and

high voltage analog circuitry.

The AD420 can also provide a voltage output instead of a cur-

rent loop output if desired. The addition of a single external

amplifier allows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or

± 10 V.

The AD420 has a loop fault detection circuit that warns if the

voltage at IOUT attempts to rise above the compliance range, due

to an open-loop circuit or insufficient power supply voltage. The

FAULT DETECT is an active low open drain signal so that one

can connect several AD420s together to one pull-up resistor for

global error detection. The pull-up resistor can be tied to the

VLL pin, or an external +5 V logic supply.

The IOUT current is controlled by a PMOS transistor and

internal amplifier as shown in the functional block diagram. The

internal circuitry that develops the fault output avoids using a

comparator with “window limits” since this would require an

actual output error before the FAULT DETECT output becomes

active. Instead, the signal is generated when the internal ampli-

fier in the output stage of the AD420 has less than approximately

one volt remaining of drive capability (when the gate of the

output PMOS transistor nearly reaches ground). Thus the

FAULT DETECT output activates slightly before the compli-

ance limit is reached. Since the comparison is made within the

feedback loop of the output amplifier, the output accuracy is

maintained by its open-loop gain, and no output error occurs

before the fault detect output becomes active.

The three-wire digital interface, comprising DATA IN, CLOCK,

and LATCH, interfaces to all commonly used serial micropro-

cessors without the addition of any external glue logic. Data is

loaded into an input register under control of CLOCK and is

loaded to the DAC when LATCH is strobed. If a user wants to

minimize the number of galvanic isolators in an intrinsically safe

application, the AD420 can be configured to run in “asynchro-

nous” mode. This mode is selected by connecting the LATCH

pin to VCC through a current limiting resistor. The data must

then be combined with a start and stop bit to “frame” the infor-

mation and trigger the internal LATCH signal.

VLL 2

REF OUT 14

VCC

23

REFERENCE

4k⍀

40⍀

AD420

19 BOOST

REF IN 15

DATA OUT 10

CLEAR 6

LATCH 7

CLOCK 8

DATA IN 9

DATA I/P

REGISTER

RANGE

SELECT 1

5

RANGE 4

SELECT 2

CLOCK

16-BIT

DAC

SWITCHED

CURRENT

SOURCES

AND

FILTERING

18 IOUT

17 VOUT

1.25k⍀

3

FAULT

DETECT

16

20

21

11

OFFSET CAP 1 CAP 2 GND

TRIM

Figure 4. Functional Block Diagram

–6–

REV. F

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