UT54LVDS217-UPA データシートの表示（PDF） - Aeroflex UTMC

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UT54LVDS217-UPA

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Aeroflex UTMC 

TxIN4

1

48 TxIN3

VDD

2

TxIN5

3

47 TxIN2

46 GND

TxIN6

GND

TxIN7

TxIN8

VDD

TxIN9

4

45 TxIN1

5

44 TxIN0

6

43

N/C

7

UT54LVDS217

42

LVDS GND

8

41

TxOUT0-

9

40

TxOUT0+

TxIN10 10

GND

11

TxIN11 12

TxIN12 13

VDD

14

TxIN13 15

TxIN14 16

GND

17

TxIN15 18

39 TxOUT1-

38 TxOUT1+

37

LVDS VDD

36 LVDS GND

35 TxOUT2-

34 TxOUT2+

33 TxCLK OUT-

32

TxCLK OUT+

31 LVDS GND

TxIN16 19

TxIN17 20

VDD

21

TxIN18 22

TxIN19 23

30 PLL GND

29

PLL VDD

28 PLL GND

27 PWR DWN

26

TxCLK IN

GND

24

25

TxIN20

PIN DESCRIPTION

Pin Name I/O No.

Description

TxIN

I 21 TTL level input

TxOUT+

O

3 Positive LVDS differential data output

TxOUT-

O

3 Negative LVDS differential data output

TxCLK IN

TxCLK

OUT+

I

1 TTL level clock input. The rising edge acts

as data strobe. Pin name TxCLK IN

O

1 Positive LVDS differential clock output

TxCLK OUT- O

1 Negative LVDS differential clock output

PWR DWN

VDD

I

1 TTL level input. Assertion (low input) TRI-

STATEs the clock and data outputs, ensur-

ing low current at power down.

I

4 Power supply pins for TTL inputs and logic

GND

I

5 Ground pins for TTL inputs and logic

PLL VDD

I

1 Power supply pins for PLL

PLL GND

I

2 Ground pins for PPL

LVDS VDD

I

1 Power supply pin for LVDS output

LVDS GND

I

3 Ground pins for LVDS outputs

TxIN

0

1

2

Figure 2. UT54LVDS217 Pinout

UT54LVDS217

LVDS CABLE

MEDIA DEPENDENT DATA

(LVDS)

UT54LVDS218

RxOUT

0

1

2

CMOS/

TTL

18

19

20

TxCLK

PCB

CLOCK

(LVDS)

GND

SHIELD

Figure 3. UT54LVDS217 Typical Application

PCB

18

19

20

RxCLK

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