UT54LVDS217-UPA データシートの表示（PDF） - Aeroflex UTMC
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UT54LVDS217-UPA Datasheet PDF : 14 Pages
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AC SWITCHING CHARACTERISTICS1
(VDD = 3.0V to 3.6V; TA = -55°C to +125°C)
SYMBOL
PARAMETER
MIN
LLHT2 LVDS Low-to-High Transition Time (Figure 5)
LHLT2 LVDS High-to-Low Transition Time (Figure 5)
TPPos02 Transmitter Output Pulse Position for Bit 0 (Figure 13)
TPPos12 Transmitter Output Pulse Position for Bit 1(Figure 13)
f=75MHz
f=75MHz
-0.18
1.72
TPPos22 Transmitter Output Pulse Position for Bit 2 (Figure 13) f=75MHz
3.63
TPPos32 Transmitter Output Pulse Position for Bit 3 (Figure 13) f=75MHz
5.53
TPPos42 Transmitter Output Pulse Position for Bit 4 (Figure 13) f=75MHz
7.44
TPPos52 Transmitter Output Pulse Position for Bit 5 (Figure 13) f=75MHz
9.34
TPPos62 Transmitter Output Pulse Position for Bit 6 (Figure 13) f=75MHz
11.25
TCCS3 Channel to Channel skew (Figure 7)
TCIP TxCLK IN Period (Figure 8)
13.3
TCIH4 TxCLK IN High Time (Figure 8)
0.35Tcip
TCIL4
TSTC2
TxCLK IN Low Time (Figure 8)
TxIN Setup to TxCLK IN (Figure 8)
THTC2 TxIN Hold to TxCLK IN (Figure 8)
15MHz
75MHz
15MHz
75MHz
0.35Tcip
1.0
0.5
0.7
0.5
TCCD TxCLK IN to TxCLK OUT Delay (Figure 9)
0.5
TPLLS Transmitter Phase Lock Loop Set (Figure 10)
TPDD Transmitter Powerdown Delay (Figure 12)
Notes:
1. Recommend transistion time for TXCLK In is 1.0 to 6.0 ns (figure 6).
2. Guaranteed by characterization.
3. Channel to channel skew is defined as the difference between TPPOS max limit and TPPOS minimum limit.
4. Guaranteed by design.
MAX
1.5
1.5
0.270
2.17
4.08
5.98
7.89
9.79
11.70
0.45
66.7
0.65Tcip
0.65Tcip
2.5
10
100
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
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