V54C3128404VALS6 データシートの表示（PDF） - Mosel Vitelic Corporation

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V54C3128404VALS6

128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4

Mosel Vitelic Corporation  

MOSEL VITELIC

V54C3128(16/80/40)4V(T/S)

Block Diagram

x4 Configuration

Column Addresses

A0 - A9, A11, AP, BA0, BA1

Row Addresses

A0 - A11, BA0, BA1

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

Row decoder

Memory array

Bank 0

4096 x 2048

x 4 bit

Row decoder

Memory array

Bank 1

4096 x 2048

x 4 bit

Row decoder

Memory array

Bank 2

4096 x 2048

x 4 bit

Row decoder

Memory array

Bank 3

4096 x 2048

x 4 bit

Input buffer Output buffer

I/O1-I/O4

Control logic & timing generator

V54C3128(16/80/40)4V(T/S) Rev.1.5 March 2003

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