MU9C8K64-50TDC データシートの表示（PDF） - Music Semiconductors
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MU9C8K64-50TDC Datasheet PDF : 30 Pages
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Register Descriptions
MU9C Binary Routing Coprocessor (RCP) Family
Address register. Address Database access is controlled
through the control states on the DSC and AC12–0 lines
(/AV=HIGH) in Hardware Control mode, or through the
Instruction register in Software Control mode.
Chip Select
There are two methods of selecting an MU9C RCP:
through Hardware control inputs /CS1 and /CS2, and
through software control through the Data Select register.
Chip Select Inputs
The Chip Select lines /CS1 and /CS2 enable an MU9C
RCP to participate in a control cycle. If either /CS1 or
/CS2 are LOW the device is selected. By connecting all
the /CS1 lines together in a multi-device system, and
decoding the lines to each individual device’s /CS2 line,
control states can operate locally within a single device or
globally in all devices. Control states can be broadcast to
all devices within the system by pulling the /CS1 lines
LOW, for operations such as Write Comparand register;
individual devices can be selected to respond to a control
state such as Write at Address by pulling a single decoded
/CS2 line LOW.
Device Select Register
One dedicated line is needed per device to do local
selection of one device within a multi-device system. In
cases where control lines are at a premium, the Device
Select register can be used as the method of selection. If
Device Select Register bit DS8 is LOW, only the device or
devices whose Page Address value, held in Configuration
Register bits FR3-0, match with the Device Select Register
bits DS3–0 will be selected. Note that the match condition
of the Device Select register is ORed with the state of the
/CS1 and /CS2 lines. If DS8 is HIGH, the device remains
unselected through the Device Select register.
The conditions of the Device Select register, the /CS1 and
/CS2 lines are sampled at the time of the falling edge of /E.
In a particular MU9C RCP within a system, that CAM
will be selected under the following conditions:
(/CS1=LOW) OR (/CS2=LOW)
OR ((DS8 = LOW) AND (DS3–0 = PA3–0))
Therefore, the /CS1 lines of all devices are tied together
for global cycles that broadcast control states to all devices
within the system; then, for local cycles, an individual
device is selected by loading all the Device Select
Registers bit DS8 LOW and bits DS3–0 with the Page
Address value of the device to be selected. On a
subsequent cycle, /CS1 and /CS2 remain HIGH, and only
the device whose Page Address value matches with its
DS3–0 will respond. After an individual device has been
selected, a global Write cycle to the Device Select register
using /CS1 line is executed to select another device, or to
disable the software chip select mechanism altogether.
Vertical Cascading
A system of any practical depth can be designed by
vertically cascading MU9C RCPs. The scheme uses a
daisy chain to provide system level prioritization as well
as Match, Multiple Match, and Full flags. There are three
daisy chains: Match, Multiple Match, and Full.
When a control state is broadcast that accesses the
highest-priority matching location or Status register, the
daisy chain ensures only that the device that responds is
the one with the highest-priority match in the system. All
other devices will have their DQ31–0 lines and PA:AA
bus outputs held in high-impedance. Therefore, the Match
Flag daisy chain controls access to the system resources
for control states that are conditional on the results of the
previous Compare cycle.
During a Comparison cycle, the Match and Multiple
Match flags will not change until /E goes HIGH during
that cycle. At this time, the daisy chain starts to resolve
system-level prioritization. Once sufficient time has
elapsed for the daisy chain to be resolved, the PA:AA bus
can be enabled with /OE, and Status Register Read cycles
will access only the highest-priority matching device.
Note that the daisy chain resolves system-level
prioritization combinatorially once initiated by /E going
HIGH. Other cycles that do not affect the daisy chain or
match results can take place in the MU9C RCP while the
daisy chain is resolving, for example, WR CR, allowing
some degree of pipelining. During a Write cycle, the Full
flag will not change until /E goes HIGH during that cycle.
There is a small propagation delay per device in the daisy
chain. Alternatively, vertical cascading can be done with
external logic that provides prioritization and select lines
back into each device. The MU9C RCP architecture
supports external prioritization for cases where the daisy
chain overhead proves unacceptable. Figure 4 shows a
system in which a number of MU9C RCPs are vertically
cascaded.
Rev. 6
11
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