VES1820X データシートの表示（PDF） - Philips Electronics
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VES1820X Datasheet PDF : 40 Pages
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Philips Semiconductors
Single chip DVB-C channel receiver
Product specification
VES1820X
FUNCTIONAL DESCRIPTION
½ ADC
The VES1820X implements a 9-bit analog to digital converter. No external voltage references are required to use
the ADC.
½ PLL
The VES1820X implements a PLL used as clock multiplier by 1, 2, 3, 4, 5, 6, 7 or 8, so that the crystal can be
low frequency (fundamental tone).
½ DOWN CONVERTER AND NYQUIST FILTERS
The digital down converter performs the down conversion of the bandpass input signal into the 2 classical
quadrature I & Q channels. Then these two signals are passed through anti-alias filters and through a half
Nyquist filter having a fixed roll-off of 0.15. The digital filter gives a stop band attenuation of more than 40 dB.
½ EQUALIZER
After Nyquist filtering, the signal is fed to an equalization filter, for echo cancellation. This equalizer can be
configured as either a transversal Equalizer or a decision feedback equalizer. The following table shows some
-4
echos configuration that the VES1820X corrects with an equivalent degradation of less than 1dB @ BER = 10 .
DELAY
(nS)
50
150
and
800
1600
AMPLITUDE
(dB)
-10
-12
and
-20
-20
PHASE
worst
worst
worst
½ CARRIER RECOVERY
The carrier synchronizer implements a fully digital algorithm allowing to recover carrier frequency offsets up to
± 8 % symbol rate. A phase error detector followed by a programmable second order loop filter provides an
estimation of the carrier phase, to compensate the input carrier frequency offset.
½ CLOCK RECOVERY
A timing error detector implements an application of Gardner algorithm for digital clock recovery.
The resulting error is fed to a programmable second order loop filter, which provides a 8-bit command to the
NCO block. This one allows to determine the right sampling time instant of the input signal.
½ AUTOMATIC GAIN CONTROL
An estimation of input signal magnitude is performed and compared to a threshold value which is programmable
via the microcontroller interface. The resulting error is then filtered to produce an 10-bit command which is then
PWM encoded and provided on pin VAGC. The PWM signal can be passed through a single RC filter to control
the input gain amplifier.
½ OUTPUT INTERFACE
After carrier recovery, the demodulated output symbol must be decoded according to the constellation diagram
given by DVB standard for 16, 32, 64, 128 and 256 QAM. The resulting symbols are then differentially decoded
(DVB compliant) and serially provided to the FEC part.
½ BLOCK SYNCHRONIZATION
At demodulator output, the length of some error bursts may exceed that which can be reliably corrected by the
Reed-Solomon decoder. The implemented de-interleaving is a convolutional one (Forney) of depth 12. The first
operation consists in synchronizing the de-interleaver. This is accomplished by detecting α consecutive MPEG2
sync words (or sync ) which are present as the first byte of each packet.
1999 March 01
5
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