VES1820X データシートの表示（PDF） - Philips Electronics
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VES1820X Datasheet PDF : 40 Pages
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Philips Semiconductors
Single chip DVB-C channel receiver
Product specification
VES1820X
SYMBOL
IICDIV[1:0]
SADDR[1:0]
SDA
SCL
TEST
TRST
TDO
TCK
TDI
TMS
CTRL1
CTRL2
IT
FEL
VIP
VIM
1999 March 01
PIN NUMBER
21,22
23,24
26
25
19
35
37
33
34
36
31
32
38
39
92
91
TYPE
I
I
I/O
(5V)
I
I
I
O
(5V)
I
I
I
I/O
(5V)
O
(5V)
O
(5V)
O
(5V)
I
I
DESCRIPTION
IICDIV[1:0] allow to select the frequency of the I2C internal system
clock, depending on the crystal frequency. Internal I2C clock is a
division of XIN by 2IICDIV and must be between 6 and 20 MHz.
SADDR[1:0] are the 2 LSBs of the I2C address of the VES1820X.
The MSBs are internally set to 00010. Therefore the complete I2C
address of the VES1820X is (MSB to LSB) : 0, 0, 0, 1, 0, SADDR[1],
SADDR[0].
SDA is a bidirectional signal. It is the serial input/output of the I2C
internal block. A pull-up resistor (typically 4.7 kΩ) must be connected
between SDA and VDD for proper operation (Open Drain output).
I2C clock input. SCL should nominally be a square wave with a
maximum frequency of 400KHz. SCL is generated by the system I2C
master.
Test input pin. For normal operation of the VES1820X, TEST must
be grounded.
Test ReSeT. This active low input signal is used to reset the TAP
controller when in boundary scan mode. In normal mode of operation
TRST must be set low.
Test Data Out. This is the serial Test output pin used in boundary
scan mode. Serial Data are provided on the falling edge of TCK.
Test ClocK : an independant clock used to drive the TAP controller
when in boundary scan mode. In normal mode of operation, TCK
must be grounded.
Test Data In. The serial input for Test data and instruction when in
boundary scan mode. In normal mode of operation, TDI must be set
to GND.
Test Mode Select. This input signal provides the logic levels needed
to change the TAP controller from state to state. In normal mode of
operation, TMS must be set to VDD.
CTRL1 is equivalent to SDA I/O of VES1820X but can be tri-stated
by I2C programmation. It is actually the output of a switch controlled
by parameter BYPIIC of register TEST (index 0F16). CTRL1 is open
drain output, and therefore requires an external pull up resistor.
CTRL2 can be configured to be a control line output or to output SCL
input. This is controlled by parameter BYPIIC of register TEST (index
0F16). CTRL2 is an open drain output and therefore requires an
external pull up resistor.
InTerrupt line. This active low output interrupt line can be configured
by the I2C interface. See registers ITsel (index 3216) and ITstat
(index 3316). IT is an open drain output and therefore requires an
external pull up resistor.
By default FEL is a front-end lock indicator. In this case FEL is an
open drain output and therefore requires an external pull up resistor.
But FEL can also be configured to output a PWM signal, which value
can be programmed through the I2C interface (see register
PWMREF, index 3416).
Positive input to the A/D converter. This pin is DC biased to half-
supply through an internal resistor divider (2 x 10kΩ resistors). In
order to remain in the range of the ADC, the voltage difference
between pins VIP and VIM should be between -0.5 and 0.5 volts.
Negative input to the A/D converter. This pin is DC biased to half-
supply through an internal resistor divider (2 x 10kΩ resistors). In
order to remain in the range of the ADC, the voltage difference
between pins VIP and VIM should be between -0.5 and 0.5 volts.
8
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