VES1993 データシートの表示（PDF） - Philips Electronics

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VES1993

Single Chip Satellite Channel Receiver

Philips Electronics 

Philips Semiconductors

Single Chip Satellite Channel Receiver

Product specification

VES1993

FEATURES

• DSS and DVB-S compatible single chip

demodulator & forward error correction.

• Dual 6-bit ADC on chip.

• PLL for crystal frequency multiplication.

• Variable rate BPSK/QPSK coherent

demodulator.

• Modulation rate from 1 to 45MBaud.

• Automatic Gain Control output.

• Digital symbol timing recovery :

Acquisition range up to ±240ppm

• Digital carrier recovery :

Acquisition range up to ±12% of symbol rate

• Half Nyquist baseband filters on chip

roll-off = 0.35 for DVB and 0.2 for DSS

• Channel quality estimation.

• Viterbi decoder :

Supported rates : from 1/2 to 8/9.

Constraint length K = 7

with G1 = 1718 G2 = 1338

VBER measurement provided.

• Convolutional deinterleaver and Reed

Solomon decoder according to DVB and

DSS specifications.

• Automatic Frame Synchronization.

• Selectable DVB-S descrambling.

• I2C bus interface.

• 100-pin MQFP package.

• CMOS technology (0.35 µm 3.3V).

APPLICATIONS

• DSS receivers.

• DVB-S receivers (ETS 300-421).

• Direct Broadcast Satellite (DBS).

DESCRIPTION

The VES 1993 is a single-chip channel receiver for satellite television

reception which matches both DSS and DVB-S standards. The

device contains a dual 6-bit flash analog to digital converter, variable

rate BPSK/QPSK coherent demodulator and Forward Error

Correction functions.The ADCs directly interface with I and Q analog

baseband signals. After A to D conversion, the VES 1993 implements

a bank of cascadable filters as well as antialias and half-Nyquist

filters. Analog AGC signal is generated by an amplitude estimation

function. The VES 1993 performs clock recovery at twice the Baud

rate and achieves coherent demodulation without any feedback to

the local oscillator. Forward Error Correction is built around two error

correcting codes : a Reed-Solomon (outer code), and a Viterbi

decoder (inner code). The Reed-Solomon decoder corrects up to 8

erroneous bytes among the N bytes of one data packet.

Convolutional deinterleaver is located between the Viterbi output and

the R.S. decoder input. De-interleaver and R.S. decoder are

automatically synchronized thanks to the frame synchronisation

algorithm which uses the sync pattern present in each packet. The

VES 1993 is controlled via an I2C bus interface. The circuit operates

up to 91MHz and can process variable modulation rates, up to

45Mbaud.

The VES 1993 provides an interrupt line which can be programmed

on either events or timing information.

Designed in 0.35 CMOS technology and housed in a 100-MQFP

package, the VES 1993 operates over the commercial temperature

range.

1999 Jan 01

2

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