VES1993 データシートの表示（PDF） - Philips Electronics
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VES1993 Datasheet PDF : 16 Pages
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Philips Semiconductors
Single Chip Satellite Channel Receiver
Product specification
VES1993
INPUT – OUTPUT SIGNAL DESCRIPTION
Symbol
CLB#
XIN
XOUT
SACLK
PLLAVS
PLLAVD
I[5:0]
And
Q[5:0]
VAGC
CTRL1
CTRL2
CTRL3
CTRL4
DO[7:0]
Pin Number
78
97
96
3
99
100
6,7,8,9,10,11
16,17,18,19,20,
21
5
4
27
92
87
56,57,58,
60,64,65,
67,68
Type
I
I
O
O
I
I
I
I
O
5V
O
5V
O
5V
O
5V
I/O
5V
O
3.3V
Description
The CLB# input is asynchronous and active low, and clears the CAS
1993. When CLB# goes low, the circuit immediately enters its RESET
mode and normal operation will resume 3 XIN rising edges later after
CLB# returned high. The I2C register contents are all initialized to their
default values. The minimum width of CLB# at low level is 3 XIN clock
periods.
Crystal oscillator input pin. Typically a fundamental XTAL oscillator is
connected between the XIN and XOUT pins. (See typical application
ERROR! REFERENCE SOURCE NOT FOUND. page Error! Bookmark not
defined.).
Crystal oscillator output pin. Typically a fundamental XTAL oscillator is
connected between the XIN and XOUT pins. (See typical application
ERROR! REFERENCE SOURCE NOT FOUND. page Error! Bookmark not
defined..)
SamplingCLocK output. SACLK is nominally a square wave clock with a
maximum of 93 MHz depending on the XTAL connected between XIN
and XOUT and the multiplying factor of the PLL.
SACLK is provided in case an external A/D is used only. When the
internal A/D is used, SACLK is set to 0.
Analog ground for the PLL.
Analog positive supply voltage for the PLL. PLLAVD is typically 3.3V.
I[5:0] and Q[5:0] are the 6-bit in-phase and quadrature base-band
symbol input signals respectively, coming from an external dual A/D
converter. These signals are sampled on the rising edge of SACLK. The
input data may be in either offset binary (default) or two’s complement
format.(See TABLE 3 page 11).When not used, these 12 pins must be
grounded (use of the internal ADCs).
PWM encoded output signal for AGC. This signal is typically fed to the
AGC amplifier through a single RC network (see typical application
Error! Reference source not found. page Error! Bookmark not
defined.). The maximum signal frequency on VAGC output is SACLK /
8. The refresh frequency of AGC information is the symbol rate divided
by 2048.
ConTRoL line output. This output is directly programmable through the
I2C interface. Its default value is a logical "1".
CTRL1 is an open drain output and therefore requires an external pull-
up resistor to either VDD or VCC.
ConTRoL line output. This output is directly programmable through the
I2C interface. Its default value is a logical "0". CTRL2 is an open drain
output and therefore requires an external pull-up resistor to either VDD
or VCC.
ConTRoL Line output. This output is directly programmable through the
I2C interface. Its default value is a logical "0". CTRL3 is an open drain
output and therefore requires an external pull-up resistor to either VDD
or VCC.
ConTRoL Line input/output. This pin is directly programmable through
the I2C interface. Its default configuration is an input. A pull-up to VDD
or VCC, or a pull-down resistor to VSS must be connected to CTRL4.
Data Output bus . These 8-bit parallel data are the outputs of the VES
1993 after demodulation, Viterbi decoding, de-interleaving, RS decoding
and de-scrambling. There are 3 possible output interfaces : two parallel
and one serial (See Error! Reference source not found.,Error!
1999 Jan 01
8
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