LTC1960 データシートの表示（PDF） - Linear Technology
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LTC1960 Datasheet PDF : 28 Pages
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LTC1960
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range (Note 7), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
tONPI
Gate B1I/B2I/DCI Turn-On Time
tOFFPI Gate B1I/B2I/DCI Turn-Off Time
VPONI
Input Gate Clamp Voltage
GB1I
GB2I
GDCI
VPOFFI
Input Gate Off Voltage
GB1I
GB2I
GDCI
Logic I/O
VGS < –3V, CLOAD = 3nF (Note 5)
VGS > –1V, CLOAD = 3nF (Note 5)
ILOAD = 1µA
Highest (VBAT1 or VSCP) – VGB1I
Highest (VBAT2 or VSCP) – VGB2I
Highest (VDCIN or VSCP) – VGDCI
ILOAD = 25µA
Highest (VBAT1 or VSCP) – VGB1I
Highest (VBAT2 or VSCP) – VGB2I
Highest (VDCIN or VSCP) – VGDCI
300
µs
10
µs
4.75
6.7
7.5
V
4.75
6.7
7.5
V
4.75
6.7
7.5
V
0.18
0.25
V
0.18
0.25
V
0.18
0.25
V
IIH/IIL SSB/SCK/MOSI Input High/Low Current
VIL
SSB/MOSI/SCK Input Low Voltage
VIH
SSB/MOSI/SCK Input High Voltage
VOL
MISO Output Low Voltage
IOFF
MISO Output Off-State Leakage Current
SPI Timing (See Timing Diagram)
IOL = 1.3mA
VMISO = 5V
l –1
l
l2
l
l
1
µA
0.8
V
V
0.4
V
2
µA
TWD
Watch Dog Timer
l 1.2
2.5
4.5
sec
tSSH
SSB High Time
680
ns
tCYC
SCK Period
CLOAD = 200pF RPULLUP = 4.7k on MISO
l2
µs
tSH
SCK High Time
680
ns
tSL
SCK Low Time
680
ns
tLD
Enable Lead Time
200
ns
tLG
Enable Lag Time
200
ns
tsu
Input Data Set-Up Time
l 100
ns
tH
Input Data Hold Time
l 100
ns
tA
Access Time (From Hi-Z to Data Active on MISO)
l
125
ns
tdis
Disable Time (Hold Time to Hi-Z State on MISO)
l
125
ns
tV
Output Data Valid
CL = 200pF, RPULLUP = 4.7k on MISO
l
580
ns
tHO
Output Data Hold
l0
ns
tIr
SCK/MOSI/SSB Rise Time
0.8V to 2V
250
ns
tIf
SCK/MOSI/SSB Fall Time
2V to 0.8V
250
ns
tOf
MISO Fall Time
2V to 0.4V, CL = 200pF
l
400
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. Battery voltage must be adequate to drive gates of PowerPath
P-channel FET switches. This does not affect charging voltage of the
battery, which can be zero volts.
Note 3. See Test Circuit.
Note 4. DCIN, BAT1, BAT2 are held at 12V and GDCI, GB1I, GB2I are
forced to 10.5V. SCP is set at 12.0V to measure source current at GDCI,
GB1I and GB2I. SCP is set at 11.9V to measure sink current at GDCI, GB1I
and GB2I.
Note 5. Extrapolated from testing with CL = 50pF.
Note 6. VDAC offset is equal to the reference voltage, since
VOUT = VREF(16mV • VDAC(VALUE)/2047 + 1)
Note 7. The LTC1960C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet specified
performance at –40°C and 85°C, but is not tested at these extended
temperature limits.
Note 8. Does not apply to low current mode. Refer to “The Current DAC
Block” in the Operation section.
1960fb
5
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