L6605D データシートの表示（PDF） - STMicroelectronics

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L6605D

SMART CARD INTERFACE

STMicroelectronics 

L6605

DESCRIPTION (continued)

The diagnostic part allows to monitor failures due

to overtemperature or wrong card positioning.

The failures are internally coded and readable in-

side the STATUS REGISTER through the bidirec-

tional pin DATA configurated in output.

The antibouncing circuitry, active during card in-

sertion only, rejects ripetitive switching-on of the

power supply sections.

PIN FUNCTION

Pin

VS

VCSO

VPPIN

VPPOUT

VCSEN

SWIT CH

CS

IRQ

PRG

DATA

CK

CEXT

GND

Description

Input Power Supply voltage for VCS regulated output and for device supply.

Output regulated voltage for card supply; ICSmax = 80mA; overload protected (81 to 200mA)

Input power supply for VPP regulated voltage

Programmable output regulated voltage for memory card writing; 8 voltage levels are allowed by

means of 3 bit DAC. IPPmax = 50mA.

(Active Low) VCS supply input enable; Its value is fixed from the µP allowing or not the normal R/W

operations on the card.

Input signal produced by the reader system indicating that a card has been inserted. Internally, an

antibouncing system is provided to avoid multiple switching.

Chip select (active low). CS low level indicates an I/O operation request from µP.

Interrupt Request (Active low).

An IRQ low level indicates that a card insertion/extraction or Failure has occured.

Program (Active low).

PRG low level enables L6605 to deliver in output the VPPO level set by 3 bit DAC.

I/O pin for data exchange between µP and the device. Through this pin flow 3 bit input DAC or 2 bit

STATUS REGISTER code.

External clock.

Pin to connect an external capacitor for antibouncing delay time.

4 pins to ground.

PIN CONNECTIONS (Top view)

Powerdip 12+3+3

THERMAL DATA

Symbol

Parameter

Rth j-amb Thermal Resistance Junction to Ambient

(*) Soldered an a 35µ thick 6cm2 P.C. board copper area.

2/10

SO 12+4+4

L6605 L6605D

60

50 (*)

Unit

°C/W

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