L6605D データシートの表示（PDF） - STMicroelectronics

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L6605D

SMART CARD INTERFACE

STMicroelectronics 

L6605

±2.5%; while during line/load variation (IPP = 1mA

to 50mA; VPPI = max. 33V) the VPP range is ±5%.

An internal circuitry checks the IPP level; the pro-

tection block activates an IRQ with the proper fail-

ure code when the output current is in 51mA to

150mA range. Under the power ON/OFF thresh-

old value the logic section and the power supply

regulators are disabled.

LOGIC SECTION

L6605 includes a logic circuitry in order to protect,

both card and itself. If a failure occours an asyn-

chronous IRQ is sent to the µP; consequently the

µP forces low CS signal as I/O request. After CS

variation the µP sends also one ”data direction

bit” into DATA DIRECTION REGISTER.

Direction bit = ”0”

Pin DATA is configurated in output and the µP

reads the 2 bit STATUS REGISTER content

Code

0

1

1st bit

No insertion

Card Inserted

2nd bit

No Failure

Failure

Figure 1: Card Insertion

Failure could be overtemperature over the 2 regu-

lators (VPP, VCS).

Direction bit = ”1”

Pin DATA is configurated in input to allow the 3

bit DAC loading and than the programming of

VPPo output level voltage. (see Table 1).

During card insertion only rising edge of switch

signal is detected , while during card extraction

switch level is detected.

In card extraction mode if occours a mechanical

switch bouncing, which causes a pulse on

SWITCH input pin with duration t ≥ 50µs the

L6605 will have the 1st Status Register content

equal to ”0” and 1 ms tshadow timing like during

card insertion mode.

Bouncing on SWITCH pin with duration T<50µs

will be transparent in the Status Register.

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