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L7203 データシートの表示(PDF) - STMicroelectronics

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L7203 Datasheet PDF : 13 Pages
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L7203
Table 1. (continued)
PHS on
time µs
56.0
56.2
56.4
56.6
56.8
57.0
57.2
57.4
> 57.6
decimal
280
281
282
283
284
285
286
287
288
NPhase
bit
100011 000
100011 001
100011 010
100011 011
100011 100
100011 101
100011 110
100011 111
100100 000
Phase Shift (degree)
350
351.25
352.50
353.75
355.00
356.25
357.50
358.75
0
PHS on = tsys * 4 * Nphase
where: tsys = 50ns if fsys = 20MHz
The resulting PHASE SHIFT value is:
PHASE SHIFT = Nphase(8:3) x 10 +
Nphase(2:0) x 1.25
For istance if Nphase = 00011 110
PHASE SHIFT = 3 x 10 + 6 x 1.25 = 37.5
Low Voltage Detector
This circuit detects if VCC is lower than a fixed
threshold. If this event happens the internal logic
is resetted and the output FETS are forced in
High impedance.
Slew Rate Control Circuit
This circuit fixes the slew rate for the output stage
in order to reduce EMI.
A reference current is generated by means of an
internal reference voltage and an external resis-
tor.
The ISRC is used to fix slew rate with a linear law:
Figure 12.
Figure 13. Phase relation between OUTPUT
sinusoidal voltage (PWM_IN > 50%)
and Hall sensor signal writin Phase
shift = 0° (default value)
Hall sensor
OUT U
OUT W
OUT V
Figure 14. Phase relation between OUTPUT
sinusoidal voltage (PWM_IN > 50%)
and Hall sensor signal writing Phase
shift = 30°
Hall sensor
OUT U
OUT W
30°
VREF
+
-
ISRC =VREF /Rext
SRC
R ext
SLEW
RATE
=
RSLR/ISRC
VREF
REXT
Rext recommended value >10K
Prescaler Pin
The PRS Pin should be forced to ground when
the FSYS frequency is lower (or equal) than
20MHz and should be forced to VCC when FSYS
frequency is higher than 20MHz, in order to set
the correct timing during the inductive sense,
start up and resynchronization phases.
Example of different phase shift settings are
shown in the following pictures.
OUT V
Figure 15. Phase relation between OUTPUT
sinusoidal voltage (PWM_IN > 50%)
and Hall sensor signal writing Phase
shift = 330°
OUT U
Hall sensor
OUT V
30°
OUT W
10/13

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