L7203S データシートの表示（PDF） - STMicroelectronics
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L7203S
STMicroelectronics
L7203S Datasheet PDF : 13 Pages
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L7203
- 0, if the input value is smaller than the counter
output
- 1, if the input value is equal or greater than the
counter output
The comparator output is "adjusted" with a com-
binational logic with the 2 low significant bit of the
word to be converted in order to reach a 10 bit
precision.
The comparator output duty cycle is extended
with a half fsys period for every low bit step how
is showed in the figure 11.
Phase Shift Block
This block regulates the phase of the driving sig-
nal to control the dephasing between the Zero-
Cross signal and the voltage sinusoidal output
signal.
It is possible to demonstrate that the maximum
efficiency for the motor driving may be reached
ensuring a particular value PH of dephase be-
tween the Zero-Cross signal and the voltage out-
put signal.
The Phase Shift BLock, starting from the PHS in-
put signal synchronize the wave output with the
Zero-Cross signal to ensure the optimum
dephase.
The PHS signal expresses the phase shift
through the duration of its value according to the
following rule:
Table 1.
PHS on
time µs (Tsys = 50ns)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
16.0
16.2
16.4
16.6
16.8
17.0
17.2
17.4
decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
.
.
.
.
80
81
82
83
84
85
86
87
.
.
.
.
NPhase
bit
00000 000
00000 001
00000 010
00000 011
00000 100
00000 101
00000 110
00000 111
00001 000
00001 001
00001 010
00001 011
00001 100
00001 101
00001 110
00001 111
000010 000
000010 001
000010 010
000010 011
000010 100
000010 101
000010 110
000010 111
.
.
.
.
001010 000
001010 001
001010 010
001010 011
001010 100
001010 101
001010 110
001010 111
.
.
.
.
Phase Shift (degree)
LATCH
1.25
2.50
3.75
5.00
6.25
7.50
8.75
10
11.25
12.50
13.75
15.00
16.25
17.50
18.75
20
21.25
22.50
23.75
25.00
26.25
27.50
28.75
.
.
.
.
100
101.25
102.50
103.75
105.00
106.25
107.50
108.75
.
.
.
.
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