PM5945-UTP5 データシートの表示（PDF） - PMC-Sierra

部品番号

コンポーネント説明

メーカー

PM5945-UTP5

SONET ATM PHYSICAL INTERFACE APPLICATION BOARD FOR CAT-5 UTP

PMC-Sierra 

S TANDARD PRODUCT

PMC-Sierra, Inc.

PM5945 -UTP5

PMC-940202 ISSUE 2. APRIL 7, 1995

APP_SAPI_UTP5

______________________________________________________________________________________________

OVERVIEW

The PM5945-UTP5 (SAPI-UTP5) daughter board contains the PMC PM5345 S/UNI-

155 (SATURN User Network Interface) device, the Cypress CY7B951 SONET/SDH

Serial Transceiver (a clock and data recovery and clock synthesis device), and the

CAT-5 UTP PMD in a complete CAT-5 UTP ATM (Asynchronous Transfer Mode)

physical interface. The S/UNI is an ATM physical layer processor for a SONET

STS-3C transmission system. This daughter board has been designed to mate with

National Semiconductor Corporation's DP83300VK Vicksburg EISA adapter

motherboard to form a complete evaluation system. It is configured, monitored, and

powered through a 100 pin edge connector that mates with the Vicksburg

motherboard. The motherboard provides all of the software and decoding logic

necessary to directly access all of the registers on the SAPI-UTP5 board.

The SAPI-UTP5 line side interface deploys the National Semiconductor's DP83223

Twisted Pair FDDI Transceiver (TWISTER) device plus some magnetics to couple

signals to and from Category 5 Unshielded Twisted Pair (UTP5) cables. The

TWISTER is capable of transmitting and receiving two-level (NRZ) datastreams at

155.52 MHz. The output of the clock and data recovery unit, Cypress SONET/SDH

Serial Transceiver (CY7B951), is ac-coupled to the SUNI's bit serial input. On the

transmit side, the SUNI's PECL data outputs connect directly to the CY7B951's

serial input which buffers the data and outputs the data directly to the TWISTER. On

the receive side, the TWISTER's receive section connects to the clock and data

recovery section of the CY7B951 and uses the SUNI's bit serial input. The

CY7B951 can mux the output data to the input of the PLL and transfer back the

recovered clock and data to the input of the S/UNI for diagnostic purposes. The

cables connect to the SAPI-UTP5 board via a RJ45 jack.

The SAPI-UTP5 drop side interface uses a 100 pin edge connector. The 22V10

PLDs transform the S/UNI drop side signals to comply with the UTOPIA like signals

of the Vicksburg motherboard. The receive drop side also incorporates an

additional FIFO as the internal 4 cell FIFO of the S/UNI device is insufficient to

handle the latency time between burst cell reads by the R-FRED device on the

Vicksburg motherboard.

______________________________________________________________________________________________

1

Share Link: