PM5945-UTP5 データシートの表示（PDF） - PMC-Sierra

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PM5945-UTP5

SONET ATM PHYSICAL INTERFACE APPLICATION BOARD FOR CAT-5 UTP

PMC-Sierra 

S TANDARD PRODUCT

PMC-Sierra, Inc.

PM5945 -UTP5

PMC-940202 ISSUE 2. APRIL 7, 1995

APP_SAPI_UTP5

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CY7B951

The Cypress SONET/SDH Serial Transceiver is an integrated SONET clock and

data recovery/clock synthesis device. The internal receive PLL recovers a 155.52

MHz clock from an incoming NRZ or NRZI data and re-times the data. The receive

PLL uses a 19.44 MHz reference clock to provide a 155.52 MHz clock in the

absence of input data. The reference clock is also used to improve the PLL lock

time. The differential input data is re-timed by the recovered clock and presented as

the PECL differential output data.

The transmit section of the SONET/SDH Serial Transceiver contains a PLL that

takes a reference clock and multiplies it by 8 to produce a 155.52 MHz PECL

differential output clock. The transmit PECL differential input pair are used to buffer

the transmit PECL output of the S/UNI. This input can also be muxed into the

receive side PLL for clock and data recovery (used for diagnostic purposes).

TWISTER

The DP83223 TWISTER device is capable of transmitting and receiving either two-

level (NRZ) or three-level (MLT-3) signals. It allows links of up to 100 meters of

Category 5 Unshielded Twisted Pair (UTP5) cable and consists of a transmit and a

receive section.

The transmit section of the TWISTER contains a 100K ECL input buffer and a

Programmable Current Output Driver. The Programmable Current Output Driver in

this application is configured to output a current sourced NRZ datastream. The

transmit amplitude of the signal can be adjusted via an external resistor. The

nominal output voltage is 1.0 Volts peak to peak. An isolation transformer with 1:1

turns ratio plus a common mode choke is used to couple signals to UTP5 cable.

The receive section of the TWISTER consists of a differential input equalization

amplifier with signal detect circuitry, signal comparators with control logic, loopback

multiplexer logic and differential 100K ECL output drivers. The equalization

amplifier is set to the adaptive equalization mode. It incorporates a fixed nominal

receive input reference and compares it to the nominal transmit output amplitude to

approximate cable length and provide active compensation. The equalization

amplifier is optimized for a line voltage of 1.4 Volts peak to peak. Thus a step-up

transformer with 1:1.4 turns ratio plus a common mode choke is deployed to put the

line signal into the optimum operating range of the TWISTER's equalization

amplifier.

Line Interface

The line interface consists of the TWISTER connected to the CY7B951. To ensure

that there is a clock in the absence of incoming signal, the differential signal detect

(SD) outputs of the TWISTER are used to select between the serial and parallel

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