SY89426(1999) データシートの表示（PDF） - Micrel

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SY89426
(Rev.:1999)

SONET OC-12/OC-3 CLOCK SYNTHESIZER

Micrel 

Micrel

FUNCTIONAL BLOCK DIAGRAM

RFCK

(TTL)

SEL39

(TTL)

SEL78

(TTL)

VCCA GND

5

7

FLTRP/N

Φ/f

CHG

PUMP

622MHz

VCO

FEEDBACK DIVIDER

÷ 2/3/4

÷4

VCCO

RST

(TTL)

CK622P

(PECL)

CK622N

CK155

(PECL)

RETRFCK

(TTL)

DISC

(TTL)

ClockWorks™

SY89426

PIN DESCRIPTION

INPUTS

OUTPUTS

RFCK [Reference Clock] TTL

Reference clock IN. (38.88, 51.84 or 77.76MHz).

CK622P, CK622N [622 Clock Output] Differential PECL.

622.08MHz output clock from PLL B.

SEL39 [38.88MHz Select] TTL

CK155 [155 Clock Out] Single-ended PECL

Logic HIGH on this pin denotes a 38.88MHz input reference 155.52MHz output clock.

clock. Tie to logic LOW if input is not 38.88MHz.

SEL78 [77.76MHz Select] TTL

Logic HIGH on this pin denotes a 77.76MHz input reference

clock. Tie to logic LOW if input is not 77.76MHz.

RST [Reset] TTL

Tie to logic LOW for normal operation; logic HIGH forces reset

of internal Phase Detector & feedback dividers.

FLTRP, FLTRN [Loop Filter, Pos & Neg] Analog

Connect a series RC loop filter between these pins. The

suggested RC values are 500Ω and 0.1µF, as shown in the

Typical Application.

RETRFCK [Retimed Reference Clock Out] TTL

An output clock with the same frequency as the input Reference

Clock (RFCK) and a 45-55% duty cycle. This output is derived

by dividing the 622.08MHz output by the appropriate factor

(e.g., divide by 16 for a 38.88MHz inout reference; divide by

12 for 51.84Mhz in; or divide by 8 for 77.76MHz in).

POWER & GROUND

VCC

VCCO

GND

+5V for internal circuits.

+5V for PECL outputs.

Ground (0 volts).

DISC [Disable Clock] TTL

Logic HIGH on this pin disables the Retimed Reference Clock

output RETRFCK); if this output is not required, it is

recommended that it be disabled to reduce switching noise. A

logic LOW enables the output.

2

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