4220-22 データシートの表示（PDF） - Peregrine Semiconductor
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4220-22 Datasheet PDF : 7 Pages
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Figure 3. Pin Configuration (Top View)
VDD
1
8 RF1
CTRL 2
GND 3
RFC 4
4220
7 GND
6 GND
5 RF2
Table 2. Pin Descriptions
Pin
Pin
No.
Name
Description
1
VDD
Nominal 3 V supply connection. A
bypass capacitor (100 pF) to the ground
plane should be placed as close as
possible to the pin
2
CTRL
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
3
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
4
RFC
Common RF port for switch (Note 1)
5
RF2
RF2 port (Note 1)
6
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
7
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
8
RF1
RF1 port (Note 1)
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 VDC.
Table 3. DC Electrical Specifications
Parameter
Min Typ Max Units
VDD Power Supply Voltage
IDD Power Supply Current
(VDD = 3V, VCNTL = 3)
Control Voltage High
Control Voltage Low
2.7
0.7x VDD
3.0
3.3
V
30
40
µA
V
0.3x VDD V
PE4220
Product Specification
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Power supply voltage
-0.3 4.0
V
VI
Voltage on any input
-0.3
VDD
+ 0.3
V
TST
Storage temperature range -65 150 °C
TOP
Operating temperature
range
-40 85
°C
PIN
VESD
Input power (50Ω)
ESD voltage (Human Body
Model)
25 dBm
250
V
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. Control Logic Truth Table
Control Voltage
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Signal Path
RFC to RF1
RFC to RF2
Control Logic
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of VDD. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the VDD pin when the
control logic input voltage level exceeds VDD.)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 7
Document No. 70-0028-09 │ UltraCMOS™ RFIC Solutions
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