Z87L00 データシートの表示（PDF） - Zilog
部品番号
コンポーネント説明
メーカー
Z87L00 Datasheet PDF : 50 Pages
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Zilog
No
1,8
2,3,4,15,27,28,
29,40,52,53,54,
66,77,78,79,90
5
6,98
7
9
10
11,13,14,16,18,
19,20,22,23,23,
26,30,31,32,34,35
17,25,38,49,62,
73,84,93
36,37,39,41,42,
43,45,46,47,48,
50,51,55,56,58,59
60,61
63
65
67
68,69,70,71,72,
74,75,76
81
82
83
85,86,87
88
89
92
94
95
96
97
99
100
Table 2. 100-Pin QFP Pin Configuration
Symbol
AVDD
N/C
Function
Analog VDD
No connection
Z87000/Z87L00
Spread Spectrum Controllers
Direction
–
1
–
TX
AGND
RX
VREF
RFEON
P1[15..0]
Analog transmit IF signal
Analog ground
Analog receive IF signal
Analog reference voltage for RX signal
RF module on/off control
General-purpose I/O port 0
Output
–
Input
–
Output
Input
VDD
P0[15..0]
Digital
General-purpose I/O port 0
–
Input
ANT[1..0]
TEST
HBSW
CLKOUT
VXDATA[7..]
VXRDYB
VXSTRB
VXRWB
VXADD[2..0]
CODCLK
/RESETB
MCLK
RFTX
SYLE
RXON
RFRX
PWLV
RSSI
RF diversity antenna control
Main test mode control
Handset/bast control
Clock output to ADPCM processor
ADPCM processor data bus
ADPCM processor ready signal
ADPCM processor data strobe
ADPCM processor read/write control
ADPCM processor address bus
Clock output to codec
Reset signal
Master clock input (16.384 MHz)
RF transmit switch control
RF synthesizer load enable
Demodulator “on” indication
RF receive switch control
RF transmit power level
RF receive signal strength indicator
Input/Output
Input
Input
Output
Input
Output
Input
Input
Input
Output
Input
Input
Output
Output
Output
Output
Input
Input
DS96WRL0501
PRELIMINARY
1-7
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