STLC1502 データシートの表示（PDF） - STMicroelectronics

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STLC1502

VOICE OVER IP PROCESSOR

STMicroelectronics 

STLC1502

connected on the same external 32 bits high speed bus

• Two MII interfaces can hook directly to two 10/100 Ethernet PHYs

• Internal control hardware manages the switching and MAC processing of frames on the two Ethernet

ports

• Standard serial communication ports are available for easy device connection

• The SPI port is mainly dedicated to the CODEC control. It is compatible with the STM codecs

STLC5046, STLC5048, STW5093. It is a standard SPI port and other peripherals can be connected

to it beside the codec

• I2C port can be use to connect a LCD driver in case of IP-phone application, and a serial EEPROM

for boot coded and configuration data storage

• GPIO block includes as an alternative function a scanning key encoder for direct interface with a 6x6

keypad matrix

• Debouncing function is performed, so no overhead for the ARM controller is introduced

• UART port allows connection to a host terminal. Code downloaded through UART can be performed

during boot

• A Host Processor Interface (HPI) allows direct connection of an external control processor. The inter-

face is directly compatible with the Motorola MPC850 external bus

3.2 D950 domain

The D950 domain is a DSP machine based on the D950 core.

• The D950 core is based on Harvard architecture with separate buses for instruction (I-bus) and data

(X-bus, Y-bus)

• The internal ROM runs basic system management code and standard vocoders

G711,G723.1A,G729AB that are included in the H.323 specification

• Additional vocoders and algorithms are downloaded from the ARM side through the DPRAM

• External CODEC is connected with a standard four wires PCM bus interface

• JTAG and emulation port are available for system software/hardware testing

• DPRAM is used as a communication channel between the ARM and D950

• Control messages and voice packets are exchanged through the DPRAM

• Fax over IP support

3.3 Clock Domain

Three main clock domains are present:

• D950 and peripherals (100 MHz max)

• ARM7 and peripherals (60 MHz max)

• PCM (8.192 MHz max)

The clock base is provided by a fixed external 25MHz crystal/oscillator. A 25MHz clock output can be used

as a master clock for external Ethernet PHY devices, in 10BaseT operation.

NOTE: For 100BaseT operation, this clock may not be sufficiently stable with tight jitter requirements.

Thus the PHY’s may need their own 25 MHz crystal.

Internal PLL’s provide independent clocks to the D950 and ARM7 domain.

The ARM frequency is set by external pin, that selects between 50 MHz and 60 MHz.

The D950 frequency can be set by the ARM via Status register programming.

Four possible values are provided:

100 MHz

180 MHz

190 MHz

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